mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-26 23:04:50 +00:00
feat(nxp-clk): refactor clock enablement
Simplify the clock enablement mechanism from a usage perspective. With this new approach, enabling a clock cascades the turn-on sequence of all its parent clocks in the clock tree. Therefore, enabling the A53 clock will also turn on the A53 PLL and the oscillator that feeds it. Change-Id: Ifc2bee3e9edbb4baced34f9e809a961562f7d0a6 Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
This commit is contained in:
Ghennadi Procopciuc
parent
96e069cb8e
commit
5300040bfd
2 changed files with 127 additions and 118 deletions
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@ -14,7 +14,7 @@
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#include <s32cc-clk-modules.h>
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#include <s32cc-clk-utils.h>
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#define MAX_STACK_DEPTH (15U)
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#define MAX_STACK_DEPTH (40U)
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/* This is used for floating-point precision calculations. */
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#define FP_PRECISION (100000000UL)
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@ -52,7 +52,9 @@ static struct s32cc_clk_drv *get_drv(void)
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return &driver;
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}
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static int enable_module(const struct s32cc_clk_obj *module, unsigned int *depth);
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static int enable_module(struct s32cc_clk_obj *module,
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const struct s32cc_clk_drv *drv,
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unsigned int depth);
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static struct s32cc_clk_obj *get_clk_parent(const struct s32cc_clk_obj *module)
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{
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@ -69,33 +71,6 @@ static struct s32cc_clk_obj *get_clk_parent(const struct s32cc_clk_obj *module)
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return NULL;
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}
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static int enable_clk_module(const struct s32cc_clk_obj *module,
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const struct s32cc_clk_drv *drv,
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unsigned int *depth)
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{
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const struct s32cc_clk *clk = s32cc_obj2clk(module);
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int ret;
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ret = update_stack_depth(depth);
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if (ret != 0) {
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return ret;
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}
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if (clk == NULL) {
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return -EINVAL;
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}
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if (clk->module != NULL) {
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return enable_module(clk->module, depth);
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}
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if (clk->pclock != NULL) {
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return enable_clk_module(&clk->pclock->desc, drv, depth);
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}
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return -EINVAL;
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}
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static int get_base_addr(enum s32cc_clk_source id, const struct s32cc_clk_drv *drv,
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uintptr_t *base)
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{
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@ -160,14 +135,14 @@ static void enable_fxosc(const struct s32cc_clk_drv *drv)
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}
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}
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static int enable_osc(const struct s32cc_clk_obj *module,
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static int enable_osc(struct s32cc_clk_obj *module,
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const struct s32cc_clk_drv *drv,
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unsigned int *depth)
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unsigned int depth)
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{
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const struct s32cc_osc *osc = s32cc_obj2osc(module);
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int ret = 0;
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ret = update_stack_depth(depth);
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ret = update_stack_depth(&depth);
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if (ret != 0) {
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return ret;
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}
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@ -339,9 +314,9 @@ static int program_pll(const struct s32cc_pll *pll, uintptr_t pll_addr,
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return ret;
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}
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static int enable_pll(const struct s32cc_clk_obj *module,
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static int enable_pll(struct s32cc_clk_obj *module,
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const struct s32cc_clk_drv *drv,
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unsigned int *depth)
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unsigned int depth)
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{
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const struct s32cc_pll *pll = s32cc_obj2pll(module);
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const struct s32cc_clkmux *mux;
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@ -350,7 +325,7 @@ static int enable_pll(const struct s32cc_clk_obj *module,
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uint32_t sclk_id;
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int ret;
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ret = update_stack_depth(depth);
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ret = update_stack_depth(&depth);
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if (ret != 0) {
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return ret;
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}
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@ -440,9 +415,9 @@ static struct s32cc_clk_obj *get_pll_div_parent(const struct s32cc_clk_obj *modu
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return pdiv->parent;
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}
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static int enable_pll_div(const struct s32cc_clk_obj *module,
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static int enable_pll_div(struct s32cc_clk_obj *module,
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const struct s32cc_clk_drv *drv,
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unsigned int *depth)
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unsigned int depth)
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{
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const struct s32cc_pll_out_div *pdiv = s32cc_obj2plldiv(module);
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uintptr_t pll_addr = 0x0ULL;
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@ -450,7 +425,7 @@ static int enable_pll_div(const struct s32cc_clk_obj *module,
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uint32_t dc;
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int ret;
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ret = update_stack_depth(depth);
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ret = update_stack_depth(&depth);
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if (ret != 0) {
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return ret;
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}
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@ -582,15 +557,15 @@ static struct s32cc_clk_obj *get_mux_parent(const struct s32cc_clk_obj *module)
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return &clk->desc;
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}
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static int enable_mux(const struct s32cc_clk_obj *module,
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static int enable_mux(struct s32cc_clk_obj *module,
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const struct s32cc_clk_drv *drv,
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unsigned int *depth)
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unsigned int depth)
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{
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const struct s32cc_clkmux *mux = s32cc_obj2clkmux(module);
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const struct s32cc_clk *clk;
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int ret = 0;
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ret = update_stack_depth(depth);
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ret = update_stack_depth(&depth);
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if (ret != 0) {
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return ret;
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}
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@ -637,13 +612,13 @@ static struct s32cc_clk_obj *get_dfs_parent(const struct s32cc_clk_obj *module)
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return dfs->parent;
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}
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static int enable_dfs(const struct s32cc_clk_obj *module,
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static int enable_dfs(struct s32cc_clk_obj *module,
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const struct s32cc_clk_drv *drv,
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unsigned int *depth)
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unsigned int depth)
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{
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int ret = 0;
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ret = update_stack_depth(depth);
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ret = update_stack_depth(&depth);
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if (ret != 0) {
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return ret;
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}
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@ -802,9 +777,9 @@ get_dfs_div_parent(const struct s32cc_clk_obj *module)
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return dfs_div->parent;
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}
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static int enable_dfs_div(const struct s32cc_clk_obj *module,
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static int enable_dfs_div(struct s32cc_clk_obj *module,
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const struct s32cc_clk_drv *drv,
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unsigned int *depth)
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unsigned int depth)
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{
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const struct s32cc_dfs_div *dfs_div = s32cc_obj2dfsdiv(module);
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const struct s32cc_pll *pll;
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@ -813,7 +788,7 @@ static int enable_dfs_div(const struct s32cc_clk_obj *module,
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uint32_t mfi, mfn;
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int ret = 0;
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ret = update_stack_depth(depth);
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ret = update_stack_depth(&depth);
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if (ret != 0) {
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return ret;
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}
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@ -842,12 +817,69 @@ static int enable_dfs_div(const struct s32cc_clk_obj *module,
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return init_dfs_port(dfs_addr, dfs_div->index, mfi, mfn);
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}
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static int enable_module(const struct s32cc_clk_obj *module, unsigned int *depth)
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typedef int (*enable_clk_t)(struct s32cc_clk_obj *module,
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const struct s32cc_clk_drv *drv,
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unsigned int depth);
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static int no_enable(struct s32cc_clk_obj *module,
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const struct s32cc_clk_drv *drv,
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unsigned int depth)
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{
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return 0;
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}
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static int exec_cb_with_refcount(enable_clk_t en_cb, struct s32cc_clk_obj *mod,
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const struct s32cc_clk_drv *drv, bool leaf_node,
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unsigned int depth)
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{
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const struct s32cc_clk_drv *drv = get_drv();
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int ret = 0;
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ret = update_stack_depth(depth);
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if (mod == NULL) {
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return 0;
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}
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ret = update_stack_depth(&depth);
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if (ret != 0) {
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return ret;
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}
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/* Refcount will be updated as part of the recursivity */
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if (leaf_node) {
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return en_cb(mod, drv, depth);
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}
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if (mod->refcount == 0U) {
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ret = en_cb(mod, drv, depth);
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}
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if (ret == 0) {
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mod->refcount++;
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}
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return ret;
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}
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static struct s32cc_clk_obj *get_module_parent(const struct s32cc_clk_obj *module);
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static int enable_module(struct s32cc_clk_obj *module,
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const struct s32cc_clk_drv *drv,
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unsigned int depth)
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{
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struct s32cc_clk_obj *parent = get_module_parent(module);
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static const enable_clk_t enable_clbs[8] = {
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[s32cc_clk_t] = no_enable,
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[s32cc_osc_t] = enable_osc,
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[s32cc_pll_t] = enable_pll,
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[s32cc_pll_out_div_t] = enable_pll_div,
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[s32cc_clkmux_t] = enable_mux,
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[s32cc_shared_clkmux_t] = enable_mux,
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[s32cc_dfs_t] = enable_dfs,
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[s32cc_dfs_div_t] = enable_dfs_div,
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};
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uint32_t index;
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int ret = 0;
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ret = update_stack_depth(&depth);
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if (ret != 0) {
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return ret;
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}
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@ -856,53 +888,55 @@ static int enable_module(const struct s32cc_clk_obj *module, unsigned int *depth
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return -EINVAL;
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}
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switch (module->type) {
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case s32cc_osc_t:
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ret = enable_osc(module, drv, depth);
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break;
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case s32cc_clk_t:
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ret = enable_clk_module(module, drv, depth);
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break;
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case s32cc_pll_t:
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ret = enable_pll(module, drv, depth);
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break;
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case s32cc_pll_out_div_t:
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ret = enable_pll_div(module, drv, depth);
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break;
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case s32cc_clkmux_t:
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ret = enable_mux(module, drv, depth);
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break;
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case s32cc_shared_clkmux_t:
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ret = enable_mux(module, drv, depth);
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break;
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case s32cc_fixed_div_t:
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ret = -ENOTSUP;
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break;
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case s32cc_dfs_t:
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ret = enable_dfs(module, drv, depth);
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break;
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case s32cc_dfs_div_t:
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ret = enable_dfs_div(module, drv, depth);
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break;
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default:
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ret = -EINVAL;
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break;
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index = (uint32_t)module->type;
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if (index >= ARRAY_SIZE(enable_clbs)) {
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ERROR("Undefined module type: %d\n", module->type);
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return -EINVAL;
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}
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if (enable_clbs[index] == NULL) {
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ERROR("Undefined callback for the clock type: %d\n",
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module->type);
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return -EINVAL;
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}
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parent = get_module_parent(module);
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ret = exec_cb_with_refcount(enable_module, parent, drv,
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false, depth);
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if (ret != 0) {
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return ret;
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}
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ret = exec_cb_with_refcount(enable_clbs[index], module, drv,
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true, depth);
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if (ret != 0) {
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return ret;
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}
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return ret;
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}
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static int enable_module_with_refcount(struct s32cc_clk_obj *module,
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const struct s32cc_clk_drv *drv,
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unsigned int depth)
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{
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return exec_cb_with_refcount(enable_module, module, drv, false, depth);
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}
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static int s32cc_clk_enable(unsigned long id)
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{
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const struct s32cc_clk_drv *drv = get_drv();
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unsigned int depth = MAX_STACK_DEPTH;
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const struct s32cc_clk *clk;
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struct s32cc_clk *clk;
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clk = s32cc_get_arch_clk(id);
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if (clk == NULL) {
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return -EINVAL;
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}
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return enable_module(&clk->desc, &depth);
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return enable_module_with_refcount(&clk->desc, drv, depth);
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}
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static void s32cc_clk_disable(unsigned long id)
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@ -17,7 +17,7 @@
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#define S32CC_PERIPH_PLL_VCO_FREQ (2U * GHZ)
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#define S32CC_PERIPH_PLL_PHI3_FREQ UART_CLOCK_HZ
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static int enable_fxosc_clk(void)
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static int setup_fxosc(void)
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{
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int ret;
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@ -26,15 +26,10 @@ static int enable_fxosc_clk(void)
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return ret;
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}
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ret = clk_enable(S32CC_CLK_FXOSC);
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if (ret != 0) {
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return ret;
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}
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return ret;
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}
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static int enable_arm_pll(void)
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static int setup_arm_pll(void)
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{
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int ret;
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@ -53,20 +48,10 @@ static int enable_arm_pll(void)
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return ret;
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}
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ret = clk_enable(S32CC_CLK_ARM_PLL_VCO);
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if (ret != 0) {
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return ret;
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}
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ret = clk_enable(S32CC_CLK_ARM_PLL_PHI0);
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if (ret != 0) {
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return ret;
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}
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return ret;
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}
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static int enable_periph_pll(void)
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static int setup_periph_pll(void)
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{
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int ret;
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@ -85,16 +70,6 @@ static int enable_periph_pll(void)
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return ret;
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}
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ret = clk_enable(S32CC_CLK_PERIPH_PLL_VCO);
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if (ret != 0) {
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return ret;
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}
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ret = clk_enable(S32CC_CLK_PERIPH_PLL_PHI3);
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if (ret != 0) {
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return ret;
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}
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return ret;
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}
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@ -170,17 +145,12 @@ int s32cc_init_early_clks(void)
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s32cc_clk_register_drv();
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ret = enable_fxosc_clk();
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ret = setup_fxosc();
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if (ret != 0) {
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return ret;
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}
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ret = enable_arm_pll();
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if (ret != 0) {
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return ret;
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}
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ret = enable_periph_pll();
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ret = setup_arm_pll();
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if (ret != 0) {
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return ret;
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}
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@ -195,6 +165,11 @@ int s32cc_init_early_clks(void)
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return ret;
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}
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ret = setup_periph_pll();
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if (ret != 0) {
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return ret;
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}
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ret = enable_uart_clk();
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if (ret != 0) {
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return ret;
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