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bl1-smc-handler: Ensure the lower-order 16 bits of SPSR are programmed

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A bug recently fixed in bl2/aarch32/bl2_el3_entrypoint.S relates to
programming the lower-order 16 bits of the SPSR to populate into the CPSR
on eret.

The BL1 smc-handler code is identical and has the same shortfall in
programming the SPSR from the platform defined struct
entry_point_info->spsr.

msr spsr, r1 will only update bits f->[31:24] and c->[7:0] respectively. In
order to ensure the 16 lower-order processor mode bits x->[15:8] and
c->[7:0] this patch changes msr spsr, r1 to msr spsr_xc, r1.

This change ensures we capture the x field, which we are interested in and
not the f field which we are not.

Fixes: f3b4914be3 ('AArch32: Add generic changes in BL1')

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
This commit is contained in:
Bryan O'Donoghue 2019-03-12 12:09:51 +00:00
parent eb20f04ef3
commit 520f864e66
1 changed files with 1 additions and 1 deletions
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2
bl1/aarch32/bl1_exceptions.S
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@ -71,7 +71,7 @@ debug_loop:
*/
ldr lr, [r8, #ENTRY_POINT_INFO_PC_OFFSET]
ldr r1, [r8, #(ENTRY_POINT_INFO_PC_OFFSET + 4)]
msr spsr, r1
msr spsr_xc, r1
/* Some BL32 stages expect lr_svc to provide the BL33 entry address */
cps #MODE32_svc