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stm32mp1: add timeout detection in reset driver
This change makes the platform to panic in case of peripheral reset resource malfunction. Change-Id: I17eb9cb045b78a4e5142a8c33b744e84992d732a Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Nicolas LE BAYON <nicolas.le.bayon@st.com>
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2 changed files with 35 additions and 12 deletions
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@ -10,33 +10,53 @@
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <drivers/st/stm32mp_reset.h>
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#include <lib/mmio.h>
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#include <lib/utils_def.h>
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#define RST_CLR_OFFSET 4U
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#define RESET_TIMEOUT_US_1MS U(1000)
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static uint32_t id2reg_offset(unsigned int reset_id)
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{
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return ((reset_id & GENMASK(31, 5)) >> 5) * sizeof(uint32_t);
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}
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static uint8_t id2reg_bit_pos(unsigned int reset_id)
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{
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return (uint8_t)(reset_id & GENMASK(4, 0));
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}
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void stm32mp_reset_assert(uint32_t id)
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{
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uint32_t offset = (id / (uint32_t)__LONG_BIT) * sizeof(uintptr_t);
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uint32_t bit = id % (uint32_t)__LONG_BIT;
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uint32_t offset = id2reg_offset(id);
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uint32_t bitmsk = BIT(id2reg_bit_pos(id));
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uint64_t timeout_ref;
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uintptr_t rcc_base = stm32mp_rcc_base();
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mmio_write_32(rcc_base + offset, BIT(bit));
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while ((mmio_read_32(rcc_base + offset) & BIT(bit)) == 0U) {
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;
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mmio_write_32(rcc_base + offset, bitmsk);
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timeout_ref = timeout_init_us(RESET_TIMEOUT_US_1MS);
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while ((mmio_read_32(rcc_base + offset) & bitmsk) == 0U) {
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if (timeout_elapsed(timeout_ref)) {
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panic();
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}
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}
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}
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void stm32mp_reset_deassert(uint32_t id)
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{
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uint32_t offset = ((id / (uint32_t)__LONG_BIT) * sizeof(uintptr_t)) +
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RST_CLR_OFFSET;
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uint32_t bit = id % (uint32_t)__LONG_BIT;
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uint32_t offset = id2reg_offset(id) + RCC_RSTCLRR_OFFSET;
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uint32_t bitmsk = BIT(id2reg_bit_pos(id));
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uint64_t timeout_ref;
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uintptr_t rcc_base = stm32mp_rcc_base();
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mmio_write_32(rcc_base + offset, BIT(bit));
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while ((mmio_read_32(rcc_base + offset) & BIT(bit)) != 0U) {
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;
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mmio_write_32(rcc_base + offset, bitmsk);
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timeout_ref = timeout_init_us(RESET_TIMEOUT_US_1MS);
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while ((mmio_read_32(rcc_base + offset) & bitmsk) != 0U) {
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if (timeout_elapsed(timeout_ref)) {
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panic();
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}
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}
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}
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@ -280,6 +280,9 @@
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/* Offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
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#define RCC_MP_ENCLRR_OFFSET U(4)
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/* Offset between RCC_xxxRSTSETR and RCC_xxxRSTCLRR registers */
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#define RCC_RSTCLRR_OFFSET U(4)
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/* Fields of RCC_BDCR register */
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#define RCC_BDCR_LSEON BIT(0)
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#define RCC_BDCR_LSEBYP BIT(1)
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