From 32a87d440087e0a71765a61ec341af7cfcfbda97 Mon Sep 17 00:00:00 2001 From: Jit Loon Lim Date: Mon, 16 Oct 2023 00:19:34 +0800 Subject: [PATCH] feat(intel): enable SDMMC frontdoor load for ATF->Linux SDMMC is 1 of the boot source for Agilex5 and legacy products. By enabling this, ATF is able to read out the DTB binary and loaded it to DDR for Linux boot. Change-Id: Ida303fb43ea63013a08083ce65952c5ad4e28f93 Signed-off-by: Jit Loon Lim Signed-off-by: Sieu Mun Tang --- plat/intel/soc/agilex/platform.mk | 2 ++ plat/intel/soc/agilex5/platform.mk | 4 ++++ .../soc/common/bl2_plat_mem_params_desc.c | 18 ++++++++++++++++++ plat/intel/soc/common/socfpga_storage.c | 13 +++++++++++++ plat/intel/soc/n5x/platform.mk | 2 ++ plat/intel/soc/stratix10/platform.mk | 2 ++ 6 files changed, 41 insertions(+) diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk index 5c92f7255..2a0d110c6 100644 --- a/plat/intel/soc/agilex/platform.mk +++ b/plat/intel/soc/agilex/platform.mk @@ -76,6 +76,8 @@ BL31_SOURCES += \ plat/intel/soc/common/soc/socfpga_mailbox.c \ plat/intel/soc/common/soc/socfpga_reset_manager.c +$(eval $(call add_define,ARM_PRELOADED_DTB_BASE)) + PROGRAMMABLE_RESET_ADDRESS := 0 RESET_TO_BL2 := 1 BL2_INV_DCACHE := 0 diff --git a/plat/intel/soc/agilex5/platform.mk b/plat/intel/soc/agilex5/platform.mk index 546bc2e72..f4d3b7df8 100644 --- a/plat/intel/soc/agilex5/platform.mk +++ b/plat/intel/soc/agilex5/platform.mk @@ -99,6 +99,10 @@ USE_COHERENT_MEM := 0 CTX_INCLUDE_AARCH32_REGS := 0 ERRATA_A55_1530923 := 1 +# Don't have the Linux kernel as a BL33 image by default +ARM_LINUX_KERNEL_AS_BL33 := 0 +$(eval $(call assert_boolean,ARM_LINUX_KERNEL_AS_BL33)) +$(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33)) $(eval $(call add_define,ARM_PRELOADED_DTB_BASE)) PROGRAMMABLE_RESET_ADDRESS := 0 diff --git a/plat/intel/soc/common/bl2_plat_mem_params_desc.c b/plat/intel/soc/common/bl2_plat_mem_params_desc.c index 187c53ac7..a09fb709f 100644 --- a/plat/intel/soc/common/bl2_plat_mem_params_desc.c +++ b/plat/intel/soc/common/bl2_plat_mem_params_desc.c @@ -88,9 +88,27 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = { .image_info.image_base = PLAT_NS_IMAGE_OFFSET, .image_info.image_max_size = 0x0 + 0x40000000 - PLAT_NS_IMAGE_OFFSET, +# if ARM_LINUX_KERNEL_AS_BL33 != 0 + .next_handoff_image_id = NT_FW_CONFIG_ID, + }, + + { + .image_id = NT_FW_CONFIG_ID, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, + VERSION_2, entry_point_info_t, + NON_SECURE | NON_EXECUTABLE), + SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, + VERSION_2, image_info_t, 0), + .image_info.image_base = ARM_PRELOADED_DTB_BASE, + .image_info.image_max_size = + 0x0 + 0x40000000 - ARM_PRELOADED_DTB_BASE, .next_handoff_image_id = INVALID_IMAGE_ID, }, +#else + .next_handoff_image_id = INVALID_IMAGE_ID, + }, +# endif }; REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs) diff --git a/plat/intel/soc/common/socfpga_storage.c b/plat/intel/soc/common/socfpga_storage.c index e80f0747d..2d3d7980c 100644 --- a/plat/intel/soc/common/socfpga_storage.c +++ b/plat/intel/soc/common/socfpga_storage.c @@ -55,6 +55,12 @@ static const io_uuid_spec_t bl33_uuid_spec = { .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33, }; +# if ARM_LINUX_KERNEL_AS_BL33 != 0 +static const io_uuid_spec_t nt_fw_config_uuid_spec = { + .uuid = UUID_NT_FW_CONFIG, +}; +# endif + uintptr_t a2_lba_offset; const char a2[] = {0xa2, 0x0}; @@ -101,6 +107,13 @@ static const struct plat_io_policy policies[] = { (uintptr_t) &bl33_uuid_spec, check_fip }, +# if ARM_LINUX_KERNEL_AS_BL33 != 0 + [NT_FW_CONFIG_ID] = { + &fip_dev_handle, + (uintptr_t)&nt_fw_config_uuid_spec, + check_fip + }, +# endif [GPT_IMAGE_ID] = { &boot_dev_handle, (uintptr_t) &gpt_block_spec, diff --git a/plat/intel/soc/n5x/platform.mk b/plat/intel/soc/n5x/platform.mk index 95f076fab..29fd0eb28 100644 --- a/plat/intel/soc/n5x/platform.mk +++ b/plat/intel/soc/n5x/platform.mk @@ -46,6 +46,8 @@ BL31_SOURCES += \ plat/intel/soc/common/soc/socfpga_mailbox.c \ plat/intel/soc/common/soc/socfpga_reset_manager.c +$(eval $(call add_define,ARM_PRELOADED_DTB_BASE)) + PROGRAMMABLE_RESET_ADDRESS := 0 RESET_TO_BL2 := 1 BL2_INV_DCACHE := 0 diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk index 6bc96fb6c..b249d62aa 100644 --- a/plat/intel/soc/stratix10/platform.mk +++ b/plat/intel/soc/stratix10/platform.mk @@ -75,6 +75,8 @@ BL31_SOURCES += \ plat/intel/soc/common/soc/socfpga_mailbox.c \ plat/intel/soc/common/soc/socfpga_reset_manager.c +$(eval $(call add_define,ARM_PRELOADED_DTB_BASE)) + PROGRAMMABLE_RESET_ADDRESS := 0 RESET_TO_BL2 := 1 USE_COHERENT_MEM := 1