Djam/arm-trusted-firmware
1
0
Fork 0
mirror of https://github.com/ARM-software/arm-trusted-firmware.git synced 2025-04-19 02:54:24 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

refactor(cpus): convert Neoverse V2 to use CPU helpers

Browse source 
Convert Neoverse V2 to use CPU helpers, in this case that's
only two spots.

Change-Id: Icd250f92974e8a50c459038de7644a2e68007589
Signed-off-by: Moritz Fischer <moritzf@google.com>
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
This commit is contained in:
Moritz Fischer 2023-07-18 19:08:12 +00:00 • committed by Arvind Ram Prakash
parent 31a3da83f8
commit 5039015a9d
1 changed files with 2 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
lib/cpus/aarch64/neoverse_v2.S
View file

@ -35,8 +35,7 @@ workaround_reset_start neoverse_v2, CVE(2022,23960), WORKAROUND_CVE_2022_23960
* The Neoverse-V2 generic vectors are overridden to apply errata * The Neoverse-V2 generic vectors are overridden to apply errata
* mitigation on exception entry from lower ELs. * mitigation on exception entry from lower ELs.
*/ */
adr x0, wa_cve_vbar_neoverse_v2 override_vector_table wa_cve_vbar_neoverse_v2
msr vbar_el3, x0
#endif /* IMAGE_BL31 */ #endif /* IMAGE_BL31 */
workaround_reset_end neoverse_v2, CVE(2022,23960) workaround_reset_end neoverse_v2, CVE(2022,23960)
@ -55,10 +54,7 @@ func neoverse_v2_core_pwr_dwn
* Enable CPU power down bit in power control register * Enable CPU power down bit in power control register
* --------------------------------------------------- * ---------------------------------------------------
*/ */
mrs x0, NEOVERSE_V2_CPUPWRCTLR_EL1 sysreg_bit_set NEOVERSE_V2_CPUPWRCTLR_EL1, NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
orr x0, x0, #NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
msr NEOVERSE_V2_CPUPWRCTLR_EL1, x0
apply_erratum neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 apply_erratum neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372
isb isb