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Revert "docs(bl31): aarch64: RESET_TO_BL31_WITH_PARAMS"

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Adopted RESET_TO_BL31_WITH_PARAMS functionality in RESET_TO_BL31
in the subsequent patches hence reverted this patch.
This reverts commit ac4ac38c54.

Change-Id: I5fb8eaea47d0fd6d0171260c6d834ec8de588fad
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
This commit is contained in:
Manish V Badarkhe 2023-02-21 12:30:13 +00:00
parent 3eb8cd6093
commit 5025546c08
2 changed files with 5 additions and 17 deletions
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17
docs/design/reset-design.rst
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@ -141,26 +141,19 @@ CPU executes a modified BL31 initialization, as described below.
Platform initialization
~~~~~~~~~~~~~~~~~~~~~~~
In this configuration, when the CPU resets to BL31 there should be no parameters
that can be passed in registers by previous boot stages. Instead, the platform
code in BL31 needs to know, or be able to determine, the location of the BL32
(if required) and BL33 images and provide this information in response to the
In this configuration, when the CPU resets to BL31 there are no parameters that
can be passed in registers by previous boot stages. Instead, the platform code
in BL31 needs to know, or be able to determine, the location of the BL32 (if
required) and BL33 images and provide this information in response to the
``bl31_plat_get_next_image_ep_info()`` function.
.. note::
Some platforms that configure ``RESET_TO_BL31`` might still be able to
receive parameters in registers depending on their actual boot sequence. On
those occasions, and in addition to ``RESET_TO_BL31``, these platforms should
set ``RESET_TO_BL31_WITH_PARAMS`` to avoid the input registers from being
zeroed before entering BL31.
Additionally, platform software is responsible for carrying out any security
initialisation, for example programming a TrustZone address space controller.
This might be done by the Trusted Boot Firmware or by platform code in BL31.
--------------
*Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.*
*Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved.*
.. |Default reset code flow| image:: ../resources/diagrams/default_reset_code.png
.. |Reset code flow with programmable reset address| image:: ../resources/diagrams/reset_code_no_boot_type_check.png

5
docs/getting_started/build-options.rst
View file

@ -742,11 +742,6 @@ Common build options
entrypoint) or 1 (CPU reset to BL31 entrypoint).
The default value is 0.
- ``RESET_TO_BL31_WITH_PARAMS``: If ``RESET_TO_BL31`` has been enabled, setting
this additional option guarantees that the input registers are not cleared
therefore allowing parameters to be passed to the BL31 entrypoint.
The default value is 0.
- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided
in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector
instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1