diff --git a/plat/xilinx/versal_net/aarch64/versal_net_common.c b/plat/xilinx/versal_net/aarch64/versal_net_common.c
index 0dd019461..736581842 100644
--- a/plat/xilinx/versal_net/aarch64/versal_net_common.c
+++ b/plat/xilinx/versal_net/aarch64/versal_net_common.c
@@ -42,20 +42,28 @@ const mmap_region_t *plat_get_mmap(void)
 /* For saving cpu clock for certain platform */
 uint32_t cpu_clock;
 
-char *board_name_decode(void)
+const char *board_name_decode(void)
 {
+	const char *platform;
+
 	switch (platform_id) {
 	case VERSAL_NET_SPP:
-		return "IPP";
+		platform = "IPP";
+		break;
 	case VERSAL_NET_EMU:
-		return "EMU";
+		platform = "EMU";
+		break;
 	case VERSAL_NET_SILICON:
-		return "Silicon";
+		platform = "Silicon";
+		break;
 	case VERSAL_NET_QEMU:
-		return "QEMU";
+		platform = "QEMU";
+		break;
 	default:
-		return "Unknown";
+		platform = "Unknown";
 	}
+
+	return platform;
 }
 
 void board_detection(void)
diff --git a/plat/xilinx/versal_net/bl31_versal_net_setup.c b/plat/xilinx/versal_net/bl31_versal_net_setup.c
index faeeda086..5dd7b7fb2 100644
--- a/plat/xilinx/versal_net/bl31_versal_net_setup.c
+++ b/plat/xilinx/versal_net/bl31_versal_net_setup.c
@@ -177,16 +177,19 @@ int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler)
 {
 	static uint32_t index;
 	uint32_t i;
+	int32_t ret = 0;
 
 	/* Validate 'handler' and 'id' parameters */
 	if ((handler == NULL) || (index >= MAX_INTR_EL3)) {
-		return -EINVAL;
+		ret = -EINVAL;
+		goto exit_label;
 	}
 
 	/* Check if a handler has already been registered */
 	for (i = 0; i < index; i++) {
 		if (id == type_el3_interrupt_table[i].id) {
-			return -EALREADY;
+			ret = -EALREADY;
+			goto exit_label;
 		}
 	}
 
@@ -195,7 +198,8 @@ int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler)
 
 	index++;
 
-	return 0;
+exit_label:
+	return ret;
 }
 
 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags,
diff --git a/plat/xilinx/versal_net/include/plat_private.h b/plat/xilinx/versal_net/include/plat_private.h
index 0b82ca730..8b4020e1d 100644
--- a/plat/xilinx/versal_net/include/plat_private.h
+++ b/plat/xilinx/versal_net/include/plat_private.h
@@ -35,7 +35,7 @@ void plat_versal_net_gic_redistif_off(void);
 
 extern uint32_t cpu_clock, platform_id, platform_version;
 void board_detection(void);
-char *board_name_decode(void);
+const char *board_name_decode(void);
 uint64_t smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
 		       uint64_t x4, void *cookie, void *handle, uint64_t flags);
 int32_t sip_svc_setup_init(void);
diff --git a/plat/xilinx/versal_net/include/platform_def.h b/plat/xilinx/versal_net/include/platform_def.h
index 8cb7deb1d..a7ff84ea5 100644
--- a/plat/xilinx/versal_net/include/platform_def.h
+++ b/plat/xilinx/versal_net/include/platform_def.h
@@ -25,6 +25,9 @@
 
 #define PLATFORM_CORE_COUNT		(PLATFORM_CLUSTER_COUNT * PLATFORM_CORE_COUNT_PER_CLUSTER)
 
+#define E_INVALID_CORE_COUNT		-1
+#define E_INVALID_CLUSTER_COUNT		-3
+
 #define PLAT_MAX_PWR_LVL		U(2)
 #define PLAT_MAX_RET_STATE		U(1)
 #define PLAT_MAX_OFF_STATE		U(2)
diff --git a/plat/xilinx/versal_net/plat_psci_pm.c b/plat/xilinx/versal_net/plat_psci_pm.c
index c560c5e3e..a76832ee5 100644
--- a/plat/xilinx/versal_net/plat_psci_pm.c
+++ b/plat/xilinx/versal_net/plat_psci_pm.c
@@ -29,17 +29,18 @@ static int32_t versal_net_pwr_domain_on(u_register_t mpidr)
 {
 	int32_t cpu_id = plat_core_pos_by_mpidr(mpidr);
 	const struct pm_proc *proc;
+	int32_t ret = PSCI_E_INTERN_FAIL;
 
 	VERBOSE("%s: mpidr: 0x%lx, cpuid: %x\n",
 		__func__, mpidr, cpu_id);
 
 	if (cpu_id == -1) {
-		return PSCI_E_INTERN_FAIL;
+		goto exit_label;
 	}
 
 	proc = pm_get_proc(cpu_id);
 	if (proc == NULL) {
-		return PSCI_E_INTERN_FAIL;
+		goto exit_label;
 	}
 
 	(void)pm_req_wakeup(proc->node_id, (versal_net_sec_entry & 0xFFFFFFFFU) | 0x1U,
@@ -48,7 +49,10 @@ static int32_t versal_net_pwr_domain_on(u_register_t mpidr)
 	/* Clear power down request */
 	pm_client_wakeup(proc);
 
-	return PSCI_E_SUCCESS;
+	ret = PSCI_E_SUCCESS;
+
+exit_label:
+	return ret;
 }
 
 /**
@@ -64,7 +68,7 @@ static void versal_net_pwr_domain_off(const psci_power_state_t *target_state)
 	const struct pm_proc *proc = pm_get_proc(cpu_id);
 
 	if (proc == NULL) {
-		return;
+		goto exit_label;
 	}
 
 	for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
@@ -94,6 +98,9 @@ static void versal_net_pwr_domain_off(const psci_power_state_t *target_state)
 					      SECURE_FLAG);
 		}
 	}
+
+exit_label:
+	return;
 }
 
 /**
@@ -148,7 +155,7 @@ static void versal_net_pwr_domain_suspend(const psci_power_state_t *target_state
 	const struct pm_proc *proc = pm_get_proc(cpu_id);
 
 	if (proc == NULL) {
-		return;
+		goto exit_label;
 	}
 
 	for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
@@ -170,6 +177,9 @@ static void versal_net_pwr_domain_suspend(const psci_power_state_t *target_state
 			SECURE_FLAG);
 
 	/* TODO: disable coherency */
+
+exit_label:
+	return;
 }
 
 static void versal_net_pwr_domain_on_finish(const psci_power_state_t *target_state)
@@ -195,7 +205,7 @@ static void versal_net_pwr_domain_suspend_finish(const psci_power_state_t *targe
 	const struct pm_proc *proc = pm_get_proc(cpu_id);
 
 	if (proc == NULL) {
-		return;
+		goto exit_label;
 	}
 
 	for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
@@ -214,6 +224,9 @@ static void versal_net_pwr_domain_suspend_finish(const psci_power_state_t *targe
 	}
 
 	plat_arm_gic_cpuif_enable();
+
+exit_label:
+	return;
 }
 
 /**
@@ -244,6 +257,8 @@ static void __dead2 versal_net_system_off(void)
 static int32_t versal_net_validate_power_state(unsigned int power_state,
 					       psci_power_state_t *req_state)
 {
+	int32_t ret = PSCI_E_INVALID_PARAMS;
+
 	VERBOSE("%s: power_state: 0x%x\n", __func__, power_state);
 
 	uint32_t pstate = psci_get_pstate_type(power_state);
@@ -258,11 +273,11 @@ static int32_t versal_net_validate_power_state(unsigned int power_state,
 	}
 
 	/* We expect the 'state id' to be zero */
-	if (psci_get_pstate_id(power_state) != 0U) {
-		return PSCI_E_INVALID_PARAMS;
+	if (psci_get_pstate_id(power_state) == 0U) {
+		ret = PSCI_E_SUCCESS;
 	}
 
-	return PSCI_E_SUCCESS;
+	return ret;
 }
 
 /**
diff --git a/plat/xilinx/versal_net/plat_topology.c b/plat/xilinx/versal_net/plat_topology.c
index 4e2d36ee4..ef5c42661 100644
--- a/plat/xilinx/versal_net/plat_topology.c
+++ b/plat/xilinx/versal_net/plat_topology.c
@@ -41,6 +41,7 @@ const uint8_t *plat_get_power_domain_tree_desc(void)
 int32_t plat_core_pos_by_mpidr(u_register_t mpidr)
 {
 	uint32_t cluster_id, cpu_id;
+	int32_t ret;
 
 	mpidr &= MPIDR_AFFINITY_MASK;
 
@@ -48,7 +49,8 @@ int32_t plat_core_pos_by_mpidr(u_register_t mpidr)
 	cpu_id = (uint32_t)MPIDR_AFFLVL1_VAL(mpidr);
 
 	if (cluster_id >= PLATFORM_CLUSTER_COUNT) {
-		return -3;
+		ret = E_INVALID_CLUSTER_COUNT;
+		goto exit_label;
 	}
 
 	/*
@@ -56,8 +58,11 @@ int32_t plat_core_pos_by_mpidr(u_register_t mpidr)
 	 * one of the two clusters present on the platform.
 	 */
 	if (cpu_id >= PLATFORM_CORE_COUNT_PER_CLUSTER) {
-		return -1;
+		ret = E_INVALID_CORE_COUNT;
+	} else {
+		ret = (int32_t)(cpu_id + (cluster_id * PLATFORM_CORE_COUNT_PER_CLUSTER));
 	}
 
-	return (int32_t)(cpu_id + (cluster_id * PLATFORM_CORE_COUNT_PER_CLUSTER));
+exit_label:
+	return ret;
 }