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Merge "fix(plat/marvell/a3720/uart): fix UART clock rate value and divisor calculation" into integration
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commit
4fe55a2fd8
2 changed files with 3 additions and 2 deletions
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@ -45,8 +45,9 @@ func console_a3700_core_init
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cbz w2, init_fail
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cbz w2, init_fail
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/* Program the baudrate */
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/* Program the baudrate */
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/* Divisor = Uart clock / (16 * baudrate) */
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/* Divisor = Round(Uartclock / (16 * baudrate)) */
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lsl w2, w2, #4
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lsl w2, w2, #4
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add w1, w1, w2, lsr #1
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udiv w2, w1, w2
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udiv w2, w1, w2
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and w2, w2, #0x3ff
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and w2, w2, #0x3ff
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@ -164,7 +164,7 @@
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* PL011 related constants
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* PL011 related constants
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*/
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*/
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#define PLAT_MARVELL_BOOT_UART_BASE (MVEBU_REGS_BASE + 0x12000)
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#define PLAT_MARVELL_BOOT_UART_BASE (MVEBU_REGS_BASE + 0x12000)
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#define PLAT_MARVELL_BOOT_UART_CLK_IN_HZ 25804800
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#define PLAT_MARVELL_BOOT_UART_CLK_IN_HZ 25000000
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#define PLAT_MARVELL_CRASH_UART_BASE PLAT_MARVELL_BOOT_UART_BASE
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#define PLAT_MARVELL_CRASH_UART_BASE PLAT_MARVELL_BOOT_UART_BASE
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#define PLAT_MARVELL_CRASH_UART_CLK_IN_HZ PLAT_MARVELL_BOOT_UART_CLK_IN_HZ
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#define PLAT_MARVELL_CRASH_UART_CLK_IN_HZ PLAT_MARVELL_BOOT_UART_CLK_IN_HZ
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