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feat(intel): add in QSPI ECC for Linux

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Add QSPI ECC new opcodes for Linux to access to SDM register

Change-Id: If9ac35afdddb91db6bad6b474060cd001f6d89e6
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
This commit is contained in:
Jit Loon Lim 2023-09-07 16:44:07 +08:00 • committed by Sieu Mun Tang
parent 11f99e8df5
commit 4d122e5f19
4 changed files with 36 additions and 3 deletions
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15
plat/intel/soc/agilex5/include/agilex5_system_manager.h
View file

@ -143,6 +143,18 @@
#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_8 0x278
#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_9 0x27C
/* QSPI ECC from SDM register */
#define SOCFPGA_ECC_QSPI_CTRL 0x08
#define SOCFPGA_ECC_QSPI_ERRINTEN 0x10
#define SOCFPGA_ECC_QSPI_ERRINTENS 0x14
#define SOCFPGA_ECC_QSPI_ERRINTENR 0x18
#define SOCFPGA_ECC_QSPI_INTMODE 0x1C
#define SOCFPGA_ECC_QSPI_INTSTAT 0x20
#define SOCFPGA_ECC_QSPI_INTTEST 0x24
#define SOCFPGA_ECC_QSPI_ECC_ACCCTRL 0x78
#define SOCFPGA_ECC_QSPI_ECC_STARTACC 0x7C
#define SOCFPGA_ECC_QSPI_ECC_WDCTRL 0x80
#define DMA0_STREAM_CTRL_REG 0x10D1217C
#define DMA1_STREAM_CTRL_REG 0x10D12180
#define SDM_STREAM_CTRL_REG 0x10D12184
@ -187,9 +199,10 @@
#define RMMUSECSID_REG_VAL BIT(5)
/* Macros */
#define SOCFPGA_ECC_QSPI(_reg) (SOCFPGA_ECC_QSPI_REG_BASE \
+ (SOCFPGA_ECC_QSPI_##_reg))
#define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \
+ (SOCFPGA_SYSMGR_##_reg))
#define ENABLE_STREAMID WSTREAMIDEN_REG_CTRL \
| RSTREAMIDEN_REG_CTRL
#define ENABLE_STREAMID_SECURE_TX WSTREAMIDEN_REG_CTRL \

1
plat/intel/soc/agilex5/include/socfpga_plat_def.h
View file

@ -48,6 +48,7 @@
#define SOCFPGA_SYSMGR_REG_BASE 0x10d12000
#define SOCFPGA_PINMUX_REG_BASE 0x10d13000
#define SOCFPGA_NAND_REG_BASE 0x10B80000
#define SOCFPGA_ECC_QSPI_REG_BASE 0x10A22000
#define SOCFPGA_L4_PER_SCR_REG_BASE 0x10d21000
#define SOCFPGA_L4_SYS_SCR_REG_BASE 0x10d21100

1
plat/intel/soc/common/include/socfpga_system_manager.h
View file

@ -14,7 +14,6 @@
#define SOCFPGA_SYSMGR_SDMMC 0x28
/* Field Masking */
#define SYSMGR_SDMMC_DRVSEL(x) (((x) & 0x7) << 0)
#define SYSMGR_SDMMC_SMPLSEL(x) (((x) & 0x7) << 4)

20
plat/intel/soc/common/socfpga_sip_svc.c
View file

@ -423,6 +423,16 @@ static int is_out_of_sec_range(uint64_t reg_addr)
case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1)): /* BOOT_SCRATCH_COLD1 */
case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8)): /* BOOT_SCRATCH_COLD8 */
case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_9)): /* BOOT_SCRATCH_COLD9 */
case(SOCFPGA_ECC_QSPI(CTRL)): /* ECC_QSPI_CTRL */
case(SOCFPGA_ECC_QSPI(ERRINTEN)): /* ECC_QSPI_ERRINTEN */
case(SOCFPGA_ECC_QSPI(ERRINTENS)): /* ECC_QSPI_ERRINTENS */
case(SOCFPGA_ECC_QSPI(ERRINTENR)): /* ECC_QSPI_ERRINTENR */
case(SOCFPGA_ECC_QSPI(INTMODE)): /* ECC_QSPI_INTMODE */
case(SOCFPGA_ECC_QSPI(ECC_ACCCTRL)): /* ECC_QSPI_ECC_ACCCTRL */
case(SOCFPGA_ECC_QSPI(ECC_STARTACC)): /* ECC_QSPI_ECC_STARTACC */
case(SOCFPGA_ECC_QSPI(ECC_WDCTRL)): /* ECC_QSPI_ECC_WDCTRL */
case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */
case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */
return 0;
#endif
default:
@ -451,7 +461,17 @@ uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val,
return INTEL_SIP_SMC_STATUS_ERROR;
}
switch (reg_addr) {
#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */
case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */
mmio_write_16(reg_addr, val);
break;
#endif
default:
mmio_write_32(reg_addr, val);
break;
}
return intel_secure_reg_read(reg_addr, retval);
}