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fix(cpu): correct Demeter CPU name
This patch changes Cortex Demeter to Neoverse Demeter. Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I7306d09ca60e101d0a96c9ceff9845422d75c160
This commit is contained in:
johpow01
John
parent
65da2f2af7
commit
4cb576a0c5
3 changed files with 31 additions and 31 deletions
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@ -4,20 +4,20 @@
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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#ifndef CORTEX_DEMETER_H
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#ifndef NEOVERSE_DEMETER_H
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#define CORTEX_DEMETER_H
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#define NEOVERSE_DEMETER_H
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#define CORTEX_DEMETER_MIDR U(0x410FD4F0)
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#define NEOVERSE_DEMETER_MIDR U(0x410FD4F0)
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/*******************************************************************************
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/*******************************************************************************
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* CPU Extended Control register specific definitions
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* CPU Extended Control register specific definitions
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******************************************************************************/
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******************************************************************************/
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#define CORTEX_DEMETER_CPUECTLR_EL1 S3_0_C15_C1_4
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#define NEOVERSE_DEMETER_CPUECTLR_EL1 S3_0_C15_C1_4
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/*******************************************************************************
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/*******************************************************************************
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* CPU Power Control register specific definitions
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* CPU Power Control register specific definitions
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******************************************************************************/
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******************************************************************************/
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#define CORTEX_DEMETER_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define NEOVERSE_DEMETER_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_DEMETER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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#define NEOVERSE_DEMETER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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#endif /* CORTEX_DEMETER_H */
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#endif /* NEOVERSE_DEMETER_H */
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@ -7,54 +7,54 @@
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#include <arch.h>
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#include <arch.h>
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#include <asm_macros.S>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <common/bl_common.h>
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#include <cortex_demeter.h>
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#include <neoverse_demeter.h>
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#include <cpu_macros.S>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include <plat_macros.S>
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/* Hardware handled coherency */
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex Demeter must be compiled with HW_ASSISTED_COHERENCY enabled"
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#error "Neoverse Demeter must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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#endif
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/* 64-bit only core */
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Cortex Demeter supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#error "Neoverse Demeter supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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#endif
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/* ----------------------------------------------------
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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* ----------------------------------------------------
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*/
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*/
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func cortex_demeter_core_pwr_dwn
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func neoverse_demeter_core_pwr_dwn
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/* ---------------------------------------------------
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* Enable CPU power down bit in power control register
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* ---------------------------------------------------
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* ---------------------------------------------------
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*/
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*/
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mrs x0, CORTEX_DEMETER_CPUPWRCTLR_EL1
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mrs x0, NEOVERSE_DEMETER_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_DEMETER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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orr x0, x0, #NEOVERSE_DEMETER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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msr CORTEX_DEMETER_CPUPWRCTLR_EL1, x0
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msr NEOVERSE_DEMETER_CPUPWRCTLR_EL1, x0
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isb
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isb
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ret
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ret
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endfunc cortex_demeter_core_pwr_dwn
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endfunc neoverse_demeter_core_pwr_dwn
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#if REPORT_ERRATA
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#if REPORT_ERRATA
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/*
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/*
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* Errata printing function for Cortex Demeter. Must follow AAPCS.
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* Errata printing function for Neoverse Demeter. Must follow AAPCS.
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*/
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*/
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func cortex_demeter_errata_report
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func neoverse_demeter_errata_report
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ret
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ret
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endfunc cortex_demeter_errata_report
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endfunc neoverse_demeter_errata_report
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#endif
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#endif
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func cortex_demeter_reset_func
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func neoverse_demeter_reset_func
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/* Disable speculative loads */
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/* Disable speculative loads */
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msr SSBS, xzr
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msr SSBS, xzr
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isb
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isb
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ret
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ret
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endfunc cortex_demeter_reset_func
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endfunc neoverse_demeter_reset_func
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/* ---------------------------------------------
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/* ---------------------------------------------
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* This function provides Cortex Demeter-
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* This function provides Neoverse Demeter-
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* specific register information for crash
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* specific register information for crash
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* reporting. It needs to return with x6
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* reporting. It needs to return with x6
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* pointing to a list of register names in ascii
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* pointing to a list of register names in ascii
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@ -62,16 +62,16 @@ endfunc cortex_demeter_reset_func
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* reported.
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* reported.
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* ---------------------------------------------
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* ---------------------------------------------
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*/
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*/
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.section .rodata.cortex_demeter_regs, "aS"
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.section .rodata.neoverse_demeter_regs, "aS"
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cortex_demeter_regs: /* The ascii list of register names to be reported */
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neoverse_demeter_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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.asciz "cpuectlr_el1", ""
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func cortex_demeter_cpu_reg_dump
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func neoverse_demeter_cpu_reg_dump
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adr x6, cortex_demeter_regs
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adr x6, neoverse_demeter_regs
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mrs x8, CORTEX_DEMETER_CPUECTLR_EL1
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mrs x8, NEOVERSE_DEMETER_CPUECTLR_EL1
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ret
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ret
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endfunc cortex_demeter_cpu_reg_dump
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endfunc neoverse_demeter_cpu_reg_dump
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declare_cpu_ops cortex_demeter, CORTEX_DEMETER_MIDR, \
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declare_cpu_ops neoverse_demeter, NEOVERSE_DEMETER_MIDR, \
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cortex_demeter_reset_func, \
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neoverse_demeter_reset_func, \
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cortex_demeter_core_pwr_dwn
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neoverse_demeter_core_pwr_dwn
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@ -130,12 +130,12 @@ else
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lib/cpus/aarch64/neoverse_n2.S \
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lib/cpus/aarch64/neoverse_n2.S \
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lib/cpus/aarch64/neoverse_e1.S \
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lib/cpus/aarch64/neoverse_e1.S \
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lib/cpus/aarch64/neoverse_v1.S \
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lib/cpus/aarch64/neoverse_v1.S \
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lib/cpus/aarch64/neoverse_demeter.S \
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lib/cpus/aarch64/cortex_a78_ae.S \
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lib/cpus/aarch64/cortex_a78_ae.S \
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lib/cpus/aarch64/cortex_a510.S \
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lib/cpus/aarch64/cortex_a510.S \
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lib/cpus/aarch64/cortex_a710.S \
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lib/cpus/aarch64/cortex_a710.S \
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lib/cpus/aarch64/cortex_makalu.S \
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lib/cpus/aarch64/cortex_makalu.S \
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lib/cpus/aarch64/cortex_makalu_elp_arm.S \
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lib/cpus/aarch64/cortex_makalu_elp_arm.S \
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lib/cpus/aarch64/cortex_demeter.S \
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lib/cpus/aarch64/cortex_a65.S \
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lib/cpus/aarch64/cortex_a65.S \
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lib/cpus/aarch64/cortex_a65ae.S \
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lib/cpus/aarch64/cortex_a65ae.S \
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lib/cpus/aarch64/cortex_a78c.S \
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lib/cpus/aarch64/cortex_a78c.S \
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