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Merge changes I1bfa797e,I0ec7a70e into integration

Browse source 
* changes:
  fix(tree): correct some typos
  fix(rockchip): use semicolon instead of comma
This commit is contained in:
Manish Pandey 2023-05-09 22:05:52 +02:00 • committed by TrustedFirmware Code Review
commit 4bd8c929b4
110 changed files with 137 additions and 137 deletions
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2
drivers/arm/css/scmi/vendor/scmi_sq.c vendored
View file

@ -15,7 +15,7 @@
#include <sq_common.h> #include <sq_common.h>
/* SCMI messge ID to get the available DRAM region */ /* SCMI message ID to get the available DRAM region */
#define SCMI_VENDOR_EXT_MEMINFO_GET_MSG 0x3 #define SCMI_VENDOR_EXT_MEMINFO_GET_MSG 0x3
#define SCMI_VENDOR_EXT_MEMINFO_GET_MSG_LEN 4 #define SCMI_VENDOR_EXT_MEMINFO_GET_MSG_LEN 4

2
drivers/arm/gic/v2/gicv2_main.c
View file

@ -252,7 +252,7 @@ void gicv2_end_of_interrupt(unsigned int id)
* Ensure the write to peripheral registers are *complete* before the write * Ensure the write to peripheral registers are *complete* before the write
* to GIC_EOIR. * to GIC_EOIR.
* *
* Note: The completion gurantee depends on various factors of system design * Note: The completion guarantee depends on various factors of system design
* and the barrier is the best core can do by which execution of further * and the barrier is the best core can do by which execution of further
* instructions waits till the barrier is alive. * instructions waits till the barrier is alive.
*/ */

2
drivers/arm/gic/v3/gic600_multichip.c
View file

@ -322,7 +322,7 @@ static void gic700_multichip_validate_data(
} }
/******************************************************************************* /*******************************************************************************
* Intialize GIC-600 and GIC-700 Multichip operation. * Initialize GIC-600 and GIC-700 Multichip operation.
******************************************************************************/ ******************************************************************************/
void gic600_multichip_init(struct gic600_multichip_data *multichip_data) void gic600_multichip_init(struct gic600_multichip_data *multichip_data)
{ {

4
drivers/brcm/emmc/emmc_chal_sd.c
View file

@ -119,7 +119,7 @@ static int32_t chal_sd_set_power(struct sd_dev *handle,
mmio_setbits_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CTRL_OFFSET, mmio_setbits_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CTRL_OFFSET,
SD4_EMMC_TOP_CTRL_SDPWR_MASK); SD4_EMMC_TOP_CTRL_SDPWR_MASK);
/* dummy write & ack to verify if the sdio is ready to send commads */ /* dummy write & ack to verify if the sdio is ready to send commands */
mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_ARG_OFFSET, 0); mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_ARG_OFFSET, 0);
mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CMD_OFFSET, 0); mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CMD_OFFSET, 0);
@ -600,7 +600,7 @@ uint32_t chal_sd_freq_2_div_ctrl_setting(uint32_t desired_freq)
if (actual_freq > desired_freq) { if (actual_freq > desired_freq) {
/* /*
* Division does not result in exact freqency match. * Division does not result in exact frequency match.
* Make sure resulting frequency does not exceed requested freq. * Make sure resulting frequency does not exceed requested freq.
*/ */
div_ctrl_setting++; div_ctrl_setting++;

6
drivers/brcm/emmc/emmc_csl_sdcard.c
View file

@ -244,7 +244,7 @@ static int abort_err(struct sd_handle *handle)
* The function handles real data transmission on both DMA and * The function handles real data transmission on both DMA and
* none DMA mode, In None DMA mode the data transfer starts * none DMA mode, In None DMA mode the data transfer starts
* when the command is sent to the card, data has to be written * when the command is sent to the card, data has to be written
* into the host contollers buffer at this time one block * into the host controllers buffer at this time one block
* at a time. * at a time.
* In DMA mode, the real data transfer is done by the DMA engine * In DMA mode, the real data transfer is done by the DMA engine
* and this functions just waits for the data transfer to complete. * and this functions just waits for the data transfer to complete.
@ -318,7 +318,7 @@ int select_blk_sz(struct sd_handle *handle, uint16_t size)
/* /*
* The function initalizes the SD/SDIO/MMC/CEATA and detects * The function initializes the SD/SDIO/MMC/CEATA and detects
* the card according to the flag of detection. * the card according to the flag of detection.
* Once this function is called, the card is put into ready state * Once this function is called, the card is put into ready state
* so application can do data transfer to and from the card. * so application can do data transfer to and from the card.
@ -393,7 +393,7 @@ int init_card(struct sd_handle *handle, int detection)
/* /*
* The function handles MMC/CEATA card initalization. * The function handles MMC/CEATA card initialization.
*/ */
int init_mmc_card(struct sd_handle *handle) int init_mmc_card(struct sd_handle *handle)
{ {

4
drivers/brcm/i2c/i2c.c
View file

@ -612,7 +612,7 @@ int i2c_probe(uint32_t bus_id, uint8_t devaddr)
* *
* Description: * Description:
* This function reads I2C data from a device without specifying * This function reads I2C data from a device without specifying
* a command regsiter. * a command register.
* *
* Parameters: * Parameters:
* bus_id - I2C bus ID * bus_id - I2C bus ID
@ -647,7 +647,7 @@ int i2c_recv_byte(uint32_t bus_id, uint8_t devaddr, uint8_t *value)
* *
* Description: * Description:
* This function send I2C data to a device without specifying * This function send I2C data to a device without specifying
* a command regsiter. * a command register.
* *
* Parameters: * Parameters:
* bus_id - I2C bus ID * bus_id - I2C bus ID

4
drivers/brcm/sotp.c
View file

@ -168,7 +168,7 @@ void sotp_mem_write(uint32_t addr, uint32_t sotp_add_ecc, uint64_t wdata)
BIT(SOTP_STATUS__FDONE)) BIT(SOTP_STATUS__FDONE))
; ;
/* Enable OTP acces by CPU */ /* Enable OTP access by CPU */
mmio_setbits_32(SOTP_PROG_CONTROL, mmio_setbits_32(SOTP_PROG_CONTROL,
BIT(SOTP_PROG_CONTROL__OTP_CPU_MODE_EN)); BIT(SOTP_PROG_CONTROL__OTP_CPU_MODE_EN));
@ -244,7 +244,7 @@ void sotp_mem_write(uint32_t addr, uint32_t sotp_add_ecc, uint64_t wdata)
/* Command done is cleared w1c */ /* Command done is cleared w1c */
mmio_setbits_32(SOTP_STATUS_1, BIT(SOTP_STATUS_1__CMD_DONE)); mmio_setbits_32(SOTP_STATUS_1, BIT(SOTP_STATUS_1__CMD_DONE));
/* disable OTP acces by CPU */ /* disable OTP access by CPU */
mmio_clrbits_32(SOTP_PROG_CONTROL, mmio_clrbits_32(SOTP_PROG_CONTROL,
BIT(SOTP_PROG_CONTROL__OTP_CPU_MODE_EN)); BIT(SOTP_PROG_CONTROL__OTP_CPU_MODE_EN));

2
drivers/marvell/comphy/phy-comphy-cp110.c
View file

@ -2053,7 +2053,7 @@ static int mvebu_cp110_comphy_usb3_power_on(uint64_t comphy_base,
mask |= HPIPE_LANE_CFG4_SSC_CTRL_MASK; mask |= HPIPE_LANE_CFG4_SSC_CTRL_MASK;
data |= 0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET; data |= 0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET;
reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask); reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask);
/* Confifure SSC amplitude */ /* Configure SSC amplitude */
mask = HPIPE_G2_TX_SSC_AMP_MASK; mask = HPIPE_G2_TX_SSC_AMP_MASK;
data = 0x1f << HPIPE_G2_TX_SSC_AMP_OFFSET; data = 0x1f << HPIPE_G2_TX_SSC_AMP_OFFSET;
reg_set(hpipe_addr + HPIPE_G2_SET_2_REG, data, mask); reg_set(hpipe_addr + HPIPE_G2_SET_2_REG, data, mask);

2
drivers/marvell/gwin.c
View file

@ -213,7 +213,7 @@ int init_gwin(int ap_index)
* remote AP should be accompanied with proper configuration to * remote AP should be accompanied with proper configuration to
* GWIN registers group and therefore the GWIN Miss feature * GWIN registers group and therefore the GWIN Miss feature
* should be set into Bypass mode, need to make sure all GWIN regions * should be set into Bypass mode, need to make sure all GWIN regions
* are defined correctly that will assure no GWIN miss occurrance * are defined correctly that will assure no GWIN miss occurrence
* JIRA-AURORA2-1630 * JIRA-AURORA2-1630
*/ */
INFO("Update GWIN miss bypass\n"); INFO("Update GWIN miss bypass\n");

2
drivers/marvell/mg_conf_cm3/mg_conf_cm3.c
View file

@ -55,7 +55,7 @@ int mg_image_load(uintptr_t src_addr, uint32_t size, int cp_index)
/* Don't release MG CM3 from reset - it will be done by next step /* Don't release MG CM3 from reset - it will be done by next step
* bootloader (e.g. U-Boot), when appriopriate device-tree setup (which * bootloader (e.g. U-Boot), when appriopriate device-tree setup (which
* has enabeld 802.3. auto-neg) will be choosen. * has enabeld 802.3. auto-neg) will be chosen.
*/ */
return 0; return 0;

2
drivers/nxp/crypto/caam/src/auth/hash.c
View file

@ -106,7 +106,7 @@ int hash_update(enum hash_algo algo, void *context, void *data_ptr,
* Function : hash_final * Function : hash_final
* Arguments : ctx - SHA context * Arguments : ctx - SHA context
* Return : SUCCESS or FAILURE * Return : SUCCESS or FAILURE
* Description : This function sets the final bit and enqueues the decriptor * Description : This function sets the final bit and enqueues the descriptor
***************************************************************************/ ***************************************************************************/
int hash_final(enum hash_algo algo, void *context, void *hash_ptr, int hash_final(enum hash_algo algo, void *context, void *hash_ptr,
unsigned int hash_len) unsigned int hash_len)

2
drivers/nxp/crypto/caam/src/hw_key_blob.c
View file

@ -18,7 +18,7 @@
#include "sec_hw_specific.h" #include "sec_hw_specific.h"
/* Callback function after Instantiation decsriptor is submitted to SEC /* Callback function after Instantiation descriptor is submitted to SEC
*/ */
static void blob_done(uint32_t *desc, uint32_t status, void *arg, static void blob_done(uint32_t *desc, uint32_t status, void *arg,
void *job_ring) void *job_ring)

4
drivers/nxp/crypto/caam/src/rng.c
View file

@ -17,7 +17,7 @@
#include "sec_hw_specific.h" #include "sec_hw_specific.h"
/* Callback function after Instantiation decsriptor is submitted to SEC */ /* Callback function after Instantiation descriptor is submitted to SEC */
static void rng_done(uint32_t *desc, uint32_t status, void *arg, static void rng_done(uint32_t *desc, uint32_t status, void *arg,
void *job_ring) void *job_ring)
{ {
@ -183,7 +183,7 @@ int hw_rng_instantiate(void)
/*if instantiate_rng(...) fails, the loop will rerun /*if instantiate_rng(...) fails, the loop will rerun
*and the kick_trng(...) function will modify the *and the kick_trng(...) function will modify the
*upper and lower limits of the entropy sampling *upper and lower limits of the entropy sampling
*interval, leading to a sucessful initialization of *interval, leading to a successful initialization of
*/ */
ret = instantiate_rng(); ret = instantiate_rng();
} while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX)); } while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));

4
drivers/nxp/ddr/nxp-ddr/ddr.c
View file

@ -293,7 +293,7 @@ static int cal_odt(const unsigned int clk,
} }
if (pdodt == NULL) { if (pdodt == NULL) {
ERROR("Error determing ODT.\n"); ERROR("Error determining ODT.\n");
return -EINVAL; return -EINVAL;
} }
@ -916,7 +916,7 @@ long long dram_init(struct ddr_info *priv
debug("Program controller registers\n"); debug("Program controller registers\n");
ret = write_ddrc_regs(priv); ret = write_ddrc_regs(priv);
if (ret != 0) { if (ret != 0) {
ERROR("Programing DDRC error\n"); ERROR("Programming DDRC error\n");
return ret; return ret;
} }

2
drivers/nxp/ddr/nxp-ddr/ddrc.c
View file

@ -346,7 +346,7 @@ int ddrc_set_regs(const unsigned long clk,
#ifdef ERRATA_DDR_A008511 #ifdef ERRATA_DDR_A008511
/* Part 1 of 2 */ /* Part 1 of 2 */
/* This erraum only applies to verion 5.2.1 */ /* This erraum only applies to version 5.2.1 */
if (get_ddrc_version(ddr) == 0x50200) { if (get_ddrc_version(ddr) == 0x50200) {
ERROR("Unsupported SoC.\n"); ERROR("Unsupported SoC.\n");
} else if (get_ddrc_version(ddr) == 0x50201) { } else if (get_ddrc_version(ddr) == 0x50201) {

16
drivers/nxp/ddr/phy-gen2/messages.h
View file

@ -144,7 +144,7 @@ static const struct phy_msg messages_1d[] = {
"PMU3: Precharge all open banks\n" "PMU3: Precharge all open banks\n"
}, },
{0x002b0002, {0x002b0002,
"PMU: Error: Dbyte %d nibble %d found mutliple working coarse delay setting for MRD/MWD\n" "PMU: Error: Dbyte %d nibble %d found multiple working coarse delay setting for MRD/MWD\n"
}, },
{0x002c0000, {0x002c0000,
"PMU4: MRD Passing Regions (coarseVal, fineLeft fineRight -> fineCenter)\n" "PMU4: MRD Passing Regions (coarseVal, fineLeft fineRight -> fineCenter)\n"
@ -536,7 +536,7 @@ static const struct phy_msg messages_1d[] = {
"PMU3: Resetting DRAM\n" "PMU3: Resetting DRAM\n"
}, },
{0x00b10000, {0x00b10000,
"PMU3: setup for RCD initalization\n" "PMU3: setup for RCD initialization\n"
}, },
{0x00b20000, {0x00b20000,
"PMU3: pmu_exit_SR from dev_init()\n" "PMU3: pmu_exit_SR from dev_init()\n"
@ -974,10 +974,10 @@ static const struct phy_msg messages_1d[] = {
"PMU0: PHY VREF @ (%d/1000) VDDQ\n" "PMU0: PHY VREF @ (%d/1000) VDDQ\n"
}, },
{0x01430002, {0x01430002,
"PMU0: initalizing phy vrefDacs to %d ExtVrefRange %x\n" "PMU0: initializing phy vrefDacs to %d ExtVrefRange %x\n"
}, },
{0x01440002, {0x01440002,
"PMU0: initalizing global vref to %d range %d\n" "PMU0: initializing global vref to %d range %d\n"
}, },
{0x01450002, {0x01450002,
"PMU4: Setting initial device vrefDQ for CS%d to MR6 = 0x%04x\n" "PMU4: Setting initial device vrefDQ for CS%d to MR6 = 0x%04x\n"
@ -1811,7 +1811,7 @@ static const struct phy_msg messages_2d[] = {
"PMU3: Precharge all open banks\n" "PMU3: Precharge all open banks\n"
}, },
{0x00be0002, {0x00be0002,
"PMU: Error: Dbyte %d nibble %d found mutliple working coarse delay setting for MRD/MWD\n" "PMU: Error: Dbyte %d nibble %d found multiple working coarse delay setting for MRD/MWD\n"
}, },
{0x00bf0000, {0x00bf0000,
"PMU4: MRD Passing Regions (coarseVal, fineLeft fineRight -> fineCenter)\n" "PMU4: MRD Passing Regions (coarseVal, fineLeft fineRight -> fineCenter)\n"
@ -2203,7 +2203,7 @@ static const struct phy_msg messages_2d[] = {
"PMU3: Resetting DRAM\n" "PMU3: Resetting DRAM\n"
}, },
{0x01440000, {0x01440000,
"PMU3: setup for RCD initalization\n" "PMU3: setup for RCD initialization\n"
}, },
{0x01450000, {0x01450000,
"PMU3: pmu_exit_SR from dev_init()\n" "PMU3: pmu_exit_SR from dev_init()\n"
@ -2641,10 +2641,10 @@ static const struct phy_msg messages_2d[] = {
"PMU0: PHY VREF @ (%d/1000) VDDQ\n" "PMU0: PHY VREF @ (%d/1000) VDDQ\n"
}, },
{0x01d60002, {0x01d60002,
"PMU0: initalizing phy vrefDacs to %d ExtVrefRange %x\n" "PMU0: initializing phy vrefDacs to %d ExtVrefRange %x\n"
}, },
{0x01d70002, {0x01d70002,
"PMU0: initalizing global vref to %d range %d\n" "PMU0: initializing global vref to %d range %d\n"
}, },
{0x01d80002, {0x01d80002,
"PMU4: Setting initial device vrefDQ for CS%d to MR6 = 0x%04x\n" "PMU4: Setting initial device vrefDQ for CS%d to MR6 = 0x%04x\n"

2
drivers/nxp/ifc/nand/ifc_nand.c
View file

@ -531,7 +531,7 @@ static int update_bbt(uint32_t idx, uint32_t blk,
return 0; return 0;
/* special case for lgb == 0 */ /* special case for lgb == 0 */
/* if blk <= lgb retrun */ /* if blk <= lgb return */
if (nand->lgb != 0 && blk <= nand->lgb) if (nand->lgb != 0 && blk <= nand->lgb)
return 0; return 0;

8
drivers/nxp/sd/sd_mmc.c
View file

@ -344,7 +344,7 @@ static int esdhc_wait_response(struct mmc *mmc, uint32_t *response)
* Function : mmc_switch_to_high_frquency * Function : mmc_switch_to_high_frquency
* Arguments : mmc - Pointer to mmc struct * Arguments : mmc - Pointer to mmc struct
* Return : SUCCESS or Error Code * Return : SUCCESS or Error Code
* Description : mmc card bellow ver 4.0 does not support high speed * Description : mmc card below ver 4.0 does not support high speed
* freq = 20 MHz * freq = 20 MHz
* Send CMD6 (CMD_SWITCH_FUNC) With args 0x03B90100 * Send CMD6 (CMD_SWITCH_FUNC) With args 0x03B90100
* Send CMD13 (CMD_SEND_STATUS) * Send CMD13 (CMD_SEND_STATUS)
@ -358,7 +358,7 @@ static int mmc_switch_to_high_frquency(struct mmc *mmc)
uint64_t start_time; uint64_t start_time;
mmc->card.bus_freq = MMC_SS_20MHZ; mmc->card.bus_freq = MMC_SS_20MHZ;
/* mmc card bellow ver 4.0 does not support high speed */ /* mmc card below ver 4.0 does not support high speed */
if (mmc->card.version < MMC_CARD_VERSION_4_X) { if (mmc->card.version < MMC_CARD_VERSION_4_X) {
return 0; return 0;
} }
@ -463,7 +463,7 @@ static int esdhc_set_data_attributes(struct mmc *mmc, uint32_t *dest_ptr,
/*************************************************************************** /***************************************************************************
* Function : esdhc_read_data_nodma * Function : esdhc_read_data_nodma
* Arguments : mmc - Pointer to mmc struct * Arguments : mmc - Pointer to mmc struct
* dest_ptr - Bufffer where read data is to be copied * dest_ptr - Buffer where read data is to be copied
* len - Length of Data to be read * len - Length of Data to be read
* Return : SUCCESS or Error Code * Return : SUCCESS or Error Code
* Description : Read data from the sdhc buffer without using DMA * Description : Read data from the sdhc buffer without using DMA
@ -698,7 +698,7 @@ static int esdhc_write_data_dma(struct mmc *mmc, uint32_t len)
/*************************************************************************** /***************************************************************************
* Function : esdhc_read_data * Function : esdhc_read_data
* Arguments : mmc - Pointer to mmc struct * Arguments : mmc - Pointer to mmc struct
* dest_ptr - Bufffer where read data is to be copied * dest_ptr - Buffer where read data is to be copied
* len - Length of Data to be read * len - Length of Data to be read
* Return : SUCCESS or Error Code * Return : SUCCESS or Error Code
* Description : Calls esdhc_read_data_nodma and clear interrupt status * Description : Calls esdhc_read_data_nodma and clear interrupt status

2
drivers/renesas/common/console/rcar_printf.c
View file

@ -24,7 +24,7 @@
/* /*
* The log is initialized and used before BL31 xlat tables are initialized, * The log is initialized and used before BL31 xlat tables are initialized,
* therefore the log memory is a device memory at that point. Make sure the * therefore the log memory is a device memory at that point. Make sure the
* memory is correclty aligned and accessed only with up-to 32bit, aligned, * memory is correctly aligned and accessed only with up-to 32bit, aligned,
* writes. * writes.
*/ */
CASSERT((RCAR_BL31_LOG_BASE & 0x7) == 0, assert_bl31_log_base_unaligned); CASSERT((RCAR_BL31_LOG_BASE & 0x7) == 0, assert_bl31_log_base_unaligned);

2
drivers/renesas/common/emmc/emmc_hal.h
View file

@ -512,7 +512,7 @@ typedef struct {
/* maximum block count which can be transferred at once */ /* maximum block count which can be transferred at once */
uint32_t max_block_count; uint32_t max_block_count;
/* maximum clock frequence in Hz supported by HW */ /* maximum clock frequency in Hz supported by HW */
uint32_t max_clock_freq; uint32_t max_clock_freq;
/* maximum data bus width supported by HW */ /* maximum data bus width supported by HW */

4
drivers/renesas/common/pfc_regs.h
View file

@ -146,10 +146,10 @@
#define GPIO_OUTDTL7 (GPIO_BASE + 0x5848U) #define GPIO_OUTDTL7 (GPIO_BASE + 0x5848U)
#define GPIO_BOTHEDGE7 (GPIO_BASE + 0x584CU) #define GPIO_BOTHEDGE7 (GPIO_BASE + 0x584CU)
/* Pin functon base address */ /* Pin function base address */
#define PFC_BASE (0xE6060000U) #define PFC_BASE (0xE6060000U)
/* Pin functon registers */ /* Pin function registers */
#define PFC_PMMR (PFC_BASE + 0x0000U) #define PFC_PMMR (PFC_BASE + 0x0000U)
#define PFC_GPSR0 (PFC_BASE + 0x0100U) #define PFC_GPSR0 (PFC_BASE + 0x0100U)
#define PFC_GPSR1 (PFC_BASE + 0x0104U) #define PFC_GPSR1 (PFC_BASE + 0x0104U)

2
drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.c
View file

@ -12,7 +12,7 @@
#include "rcar_private.h" #include "rcar_private.h"
#include "../pfc_regs.h" #include "../pfc_regs.h"
/* Pin functon bit */ /* Pin function bit */
#define GPSR0_DU_EXODDF_DU_ODDF_DISP_CDE BIT(21) #define GPSR0_DU_EXODDF_DU_ODDF_DISP_CDE BIT(21)
#define GPSR0_DU_EXVSYNC_DU_VSYNC BIT(20) #define GPSR0_DU_EXVSYNC_DU_VSYNC BIT(20)
#define GPSR0_DU_EXHSYNC_DU_HSYNC BIT(19) #define GPSR0_DU_EXHSYNC_DU_HSYNC BIT(19)

2
drivers/scmi-msg/clock.c
View file

@ -344,7 +344,7 @@ static void scmi_clock_describe_rates(struct scmi_msg *msg)
scmi_status_response(msg, status); scmi_status_response(msg, status);
} else { } else {
/* /*
* Message payload is already writen to msg->out, and * Message payload is already written to msg->out, and
* msg->out_size_out updated. * msg->out_size_out updated.
*/ */
} }

2
drivers/st/clk/stm32mp1_clk.c
View file

@ -2049,7 +2049,7 @@ int stm32mp1_clk_init(void)
stm32mp1_pll_start(i); stm32mp1_pll_start(i);
} }
/* Wait and start PLLs ouptut when ready */ /* Wait and start PLLs output when ready */
for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
if (!pllcfg_valid[i]) { if (!pllcfg_valid[i]) {
continue; continue;

2
drivers/st/crypto/stm32_pka.c
View file

@ -695,7 +695,7 @@ int stm32_pka_ecdsa_verif(void *hash, unsigned int hash_size,
mmio_setbits_32(base + _PKA_CLRFR, _PKA_IT_PROCEND); mmio_setbits_32(base + _PKA_CLRFR, _PKA_IT_PROCEND);
out: out:
/* Disable PKA (will stop all pending proccess and reset RAM) */ /* Disable PKA (will stop all pending process and reset RAM) */
pka_disable(base); pka_disable(base);
return ret; return ret;

2
drivers/st/ddr/stm32mp1_ddr.c
View file

@ -755,7 +755,7 @@ void stm32mp1_ddr_init(struct stm32mp_ddr_priv *priv,
stm32mp1_ddrphy_idone_wait(priv->phy); stm32mp1_ddrphy_idone_wait(priv->phy);
/* /*
* 12. set back registers in step 8 to the orginal values if desidered * 12. set back registers in step 8 to the original values if desidered
*/ */
stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3, stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3,
config->c_reg.pwrctl); config->c_reg.pwrctl);

2
include/arch/aarch32/arch.h
View file

@ -266,7 +266,7 @@
#define TCP10_BIT (U(1) << 10) #define TCP10_BIT (U(1) << 10)
#define HCPTR_RESET_VAL HCPTR_RES1 #define HCPTR_RESET_VAL HCPTR_RES1
/* VTTBR defintions */ /* VTTBR definitions */
#define VTTBR_RESET_VAL ULL(0x0) #define VTTBR_RESET_VAL ULL(0x0)
#define VTTBR_VMID_MASK ULL(0xff) #define VTTBR_VMID_MASK ULL(0xff)
#define VTTBR_VMID_SHIFT U(48) #define VTTBR_VMID_SHIFT U(48)

2
include/arch/aarch64/arch.h
View file

@ -755,7 +755,7 @@
#define HI_VECTOR_BASE U(0xFFFF0000) #define HI_VECTOR_BASE U(0xFFFF0000)
/* /*
* TCR defintions * TCR definitions
*/ */
#define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
#define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23))

2
include/bl31/ehf.h
View file

@ -30,7 +30,7 @@
.ehf_handler = EHF_NO_HANDLER_, \ .ehf_handler = EHF_NO_HANDLER_, \
} }
/* Macro for platforms to regiter its exception priorities */ /* Macro for platforms to register its exception priorities */
#define EHF_REGISTER_PRIORITIES(priorities, num, bits) \ #define EHF_REGISTER_PRIORITIES(priorities, num, bits) \
const ehf_priorities_t exception_data = { \ const ehf_priorities_t exception_data = { \
.num_priorities = (num), \ .num_priorities = (num), \

2
include/drivers/arm/cryptocell/712/cc_pal_types_plat.h
View file

@ -9,7 +9,7 @@
*/ */
#ifndef _CC_PAL_TYPES_PLAT_H #ifndef _CC_PAL_TYPES_PLAT_H
#define _CC_PAL_TYPES_PLAT_H #define _CC_PAL_TYPES_PLAT_H
/* Host specific types for standard (ISO-C99) compilant platforms */ /* Host specific types for standard (ISO-C99) compliant platforms */
#include <stddef.h> #include <stddef.h>
#include <stdint.h> #include <stdint.h>

2
include/drivers/arm/cryptocell/713/cc_pal_types_plat.h
View file

@ -9,7 +9,7 @@
*/ */
#ifndef _CC_PAL_TYPES_PLAT_H #ifndef _CC_PAL_TYPES_PLAT_H
#define _CC_PAL_TYPES_PLAT_H #define _CC_PAL_TYPES_PLAT_H
/* Host specific types for standard (ISO-C99) compilant platforms */ /* Host specific types for standard (ISO-C99) compliant platforms */
#include <stddef.h> #include <stddef.h>
#include <stdint.h> #include <stdint.h>

2
include/drivers/arm/gic600ae_fmu.h
View file

@ -85,7 +85,7 @@
#define FMU_BLK_PPI31 U(43) #define FMU_BLK_PPI31 U(43)
#define FMU_BLK_PRESENT_MASK U(0xFFFFFFFFFFF) #define FMU_BLK_PRESENT_MASK U(0xFFFFFFFFFFF)
/* Safety Mechamism limit */ /* Safety Mechanism limit */
#define FMU_SMID_GICD_MAX U(33) #define FMU_SMID_GICD_MAX U(33)
#define FMU_SMID_PPI_MAX U(12) #define FMU_SMID_PPI_MAX U(12)
#define FMU_SMID_ITS_MAX U(14) #define FMU_SMID_ITS_MAX U(14)

2
include/drivers/auth/crypto_mod.h
View file

@ -46,7 +46,7 @@ typedef struct crypto_lib_desc_s {
const char *name; const char *name;
/* Initialize library. This function is not expected to fail. All errors /* Initialize library. This function is not expected to fail. All errors
* must be handled inside the function, asserting or panicing in case of * must be handled inside the function, asserting or panicking in case of
* a non-recoverable error */ * a non-recoverable error */
void (*init)(void); void (*init)(void);

6
include/drivers/brcm/emmc/emmc_csl_sdprot.h
View file

@ -139,7 +139,7 @@
* The Common I/O area shall be implemented on all SDIO cards and * The Common I/O area shall be implemented on all SDIO cards and
* is accessed the the host via I/O reads and writes to function 0, * is accessed the the host via I/O reads and writes to function 0,
* the registers within the CIA are provided to enable/disable * the registers within the CIA are provided to enable/disable
* the operationo fthe i/o funciton. * the operationo fthe i/o function.
*/ */
/* cccr_sdio_rev */ /* cccr_sdio_rev */
@ -303,7 +303,7 @@
#define SBSDIO_CIS_BASE_COMMON 0x1000 #define SBSDIO_CIS_BASE_COMMON 0x1000
/* function 0(common) cis size in bytes */ /* function 0(common) cis size in bytes */
#define SBSDIO_CIS_FUNC0_LIMIT 0x020 #define SBSDIO_CIS_FUNC0_LIMIT 0x020
/* funciton 1 cis size in bytes */ /* function 1 cis size in bytes */
#define SBSDIO_CIS_SIZE_LIMIT 0x200 #define SBSDIO_CIS_SIZE_LIMIT 0x200
/* cis offset addr is < 17 bits */ /* cis offset addr is < 17 bits */
#define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
@ -313,7 +313,7 @@
/* indirect cis access (in sprom) */ /* indirect cis access (in sprom) */
/* 8 control bytes first, CIS starts from 8th uint8_t */ /* 8 control bytes first, CIS starts from 8th uint8_t */
#define SBSDIO_SPROM_CIS_OFFSET 0x8 #define SBSDIO_SPROM_CIS_OFFSET 0x8
/* sdio uint8_t mode: maximum length of one data comamnd */ /* sdio uint8_t mode: maximum length of one data command */
#define SBSDIO_BYTEMODE_DATALEN_MAX 64 #define SBSDIO_BYTEMODE_DATALEN_MAX 64
/* 4317 supports less */ /* 4317 supports less */
#define SBSDIO_BYTEMODE_DATALEN_MAX_4317 52 #define SBSDIO_BYTEMODE_DATALEN_MAX_4317 52

4
include/drivers/brcm/i2c/i2c.h
View file

@ -78,7 +78,7 @@ uint32_t i2c_get_bus_speed(uint32_t bus_id);
* *
* Description: * Description:
* This function reads I2C data from a device without specifying * This function reads I2C data from a device without specifying
* a command regsiter. * a command register.
* *
* Parameters: * Parameters:
* bus_id - I2C bus ID * bus_id - I2C bus ID
@ -95,7 +95,7 @@ int i2c_recv_byte(uint32_t bus_id, uint8_t devaddr, uint8_t *value);
* *
* Description: * Description:
* This function send I2C data to a device without specifying * This function send I2C data to a device without specifying
* a command regsiter. * a command register.
* *
* Parameters: * Parameters:
* bus_id - I2C bus ID * bus_id - I2C bus ID

2
include/drivers/nxp/crypto/caam/sec_hw_specific.h
View file

@ -221,7 +221,7 @@ typedef struct {
/* Lists the possible states for a job ring. */ /* Lists the possible states for a job ring. */
typedef enum sec_job_ring_state_e { typedef enum sec_job_ring_state_e {
SEC_JOB_RING_STATE_STARTED, /* Job ring is initialized */ SEC_JOB_RING_STATE_STARTED, /* Job ring is initialized */
SEC_JOB_RING_STATE_RESET, /* Job ring reset is in progres */ SEC_JOB_RING_STATE_RESET, /* Job ring reset is in progress */
} sec_job_ring_state_t; } sec_job_ring_state_t;
struct sec_job_ring_t { struct sec_job_ring_t {

2
include/drivers/nxp/crypto/caam/sec_jr_driver.h
View file

@ -57,7 +57,7 @@ typedef void (*user_callback) (uint32_t *desc, uint32_t status,
/* /*
* Structure encompassing a job descriptor which is to be processed * Structure encompassing a job descriptor which is to be processed
* by SEC. User should also initialise this structure with the callback * by SEC. User should also initialise this structure with the callback
* function pointer which will be called by driver after recieving proccessed * function pointer which will be called by driver after receiving proccessed
* descriptor from SEC. User data is also passed in this data structure which * descriptor from SEC. User data is also passed in this data structure which
* will be sent as an argument to the user callback function. * will be sent as an argument to the user callback function.
*/ */

2
include/drivers/nxp/dcfg/dcfg_lsch2.h
View file

@ -55,7 +55,7 @@
#define DISR5_DDRC1_MASK 0x1 #define DISR5_DDRC1_MASK 0x1
#define DISR5_OCRAM_MASK 0x40 #define DISR5_OCRAM_MASK 0x40
/* DCFG regsiters bit masks */ /* DCFG registers bit masks */
#define RCWSR0_SYS_PLL_RAT_SHIFT 25 #define RCWSR0_SYS_PLL_RAT_SHIFT 25
#define RCWSR0_SYS_PLL_RAT_MASK 0x1f #define RCWSR0_SYS_PLL_RAT_MASK 0x1f
#define RCWSR0_MEM_PLL_RAT_SHIFT 16 #define RCWSR0_MEM_PLL_RAT_SHIFT 16

2
include/lib/cpus/aarch64/generic.h
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2020, Arm Limited. All rights reserverd. * Copyright (c) 2020, Arm Limited. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */

2
lib/debugfs/debugfs_smc.c
View file

@ -54,7 +54,7 @@ static union debugfs_parms {
} parms; } parms;
/* debugfs_access_lock protects shared buffer and internal */ /* debugfs_access_lock protects shared buffer and internal */
/* FS functions from concurrent acccesses. */ /* FS functions from concurrent accesses. */
static spinlock_t debugfs_access_lock; static spinlock_t debugfs_access_lock;
static bool debugfs_initialized; static bool debugfs_initialized;

2
lib/el3_runtime/aarch64/context_mgmt.c
View file

@ -457,7 +457,7 @@ static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *e
void __init cm_init(void) void __init cm_init(void)
{ {
/* /*
* The context management library has only global data to intialize, but * The context management library has only global data to initialize, but
* that will be done when the BSS is zeroed out. * that will be done when the BSS is zeroed out.
*/ */
} }

2
lib/optee/optee_utils.c
View file

@ -180,7 +180,7 @@ int parse_optee_header(entry_point_info_t *header_ep,
/* /*
* Update "pc" value which should comes from pager image. After the * Update "pc" value which should comes from pager image. After the
* header image is parsed, it will be unuseful, and the actual * header image is parsed, it will be useless, and the actual
* execution image after BL31 is pager image. * execution image after BL31 is pager image.
*/ */
header_ep->pc = pager_image_info->image_base; header_ep->pc = pager_image_info->image_base;

2
lib/xlat_tables/aarch32/nonlpae_tables.c
View file

@ -272,7 +272,7 @@ void mmap_add_region(unsigned long long base_pa, uintptr_t base_va,
/* Make room for new region by moving other regions up by one place */ /* Make room for new region by moving other regions up by one place */
(void)memmove(mm + 1, mm, (uintptr_t)mm_last - (uintptr_t)mm); (void)memmove(mm + 1, mm, (uintptr_t)mm_last - (uintptr_t)mm);
/* Check we haven't lost the empty sentinal from the end of the array */ /* Check we haven't lost the empty sentinel from the end of the array */
assert(mm_last->size == 0U); assert(mm_last->size == 0U);
mm->base_pa = base_pa; mm->base_pa = base_pa;

2
lib/xlat_tables/xlat_tables_common.c
View file

@ -161,7 +161,7 @@ void mmap_add_region(unsigned long long base_pa, uintptr_t base_va,
/* Make room for new region by moving other regions up by one place */ /* Make room for new region by moving other regions up by one place */
(void)memmove(mm + 1, mm, (uintptr_t)mm_last - (uintptr_t)mm); (void)memmove(mm + 1, mm, (uintptr_t)mm_last - (uintptr_t)mm);
/* Check we haven't lost the empty sentinal from the end of the array */ /* Check we haven't lost the empty sentinel from the end of the array */
assert(mm_last->size == 0U); assert(mm_last->size == 0U);
mm->base_pa = base_pa; mm->base_pa = base_pa;

2
lib/xlat_tables_v2/xlat_tables_core.c
View file

@ -988,7 +988,7 @@ int mmap_add_dynamic_region_ctx(xlat_ctx_t *ctx, mmap_region_t *mm)
(uintptr_t)mm_last - (uintptr_t)mm_cursor); (uintptr_t)mm_last - (uintptr_t)mm_cursor);
/* /*
* Check we haven't lost the empty sentinal from the end of the array. * Check we haven't lost the empty sentinel from the end of the array.
* This shouldn't happen as we have checked in mmap_add_region_check * This shouldn't happen as we have checked in mmap_add_region_check
* that there is free space. * that there is free space.
*/ */

2
lib/xlat_tables_v2/xlat_tables_utils.c
View file

@ -585,7 +585,7 @@ int xlat_change_mem_attributes_ctx(const xlat_ctx_t *ctx, uintptr_t base_va,
base_va += PAGE_SIZE; base_va += PAGE_SIZE;
} }
/* Ensure that the last descriptor writen is seen by the system. */ /* Ensure that the last descriptor written is seen by the system. */
dsbish(); dsbish();
return 0; return 0;

2
plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c
View file

@ -84,7 +84,7 @@ void sp_min_plat_arch_setup(void)
(void *)hw_config_info->config_addr); (void *)hw_config_info->config_addr);
/* /*
* Preferrably we expect this address and size are page aligned, * Preferably we expect this address and size are page aligned,
* but if they are not then align it. * but if they are not then align it.
*/ */
hw_config_base_align = page_align(hw_config_info->config_addr, DOWN); hw_config_base_align = page_align(hw_config_info->config_addr, DOWN);

2
plat/arm/common/tsp/arm_tsp_setup.c
View file

@ -62,7 +62,7 @@ void tsp_platform_setup(void)
/******************************************************************************* /*******************************************************************************
* Perform the very early platform specific architectural setup here. At the * Perform the very early platform specific architectural setup here. At the
* moment this is only intializes the MMU * moment this is only initializes the MMU
******************************************************************************/ ******************************************************************************/
void tsp_plat_arch_setup(void) void tsp_plat_arch_setup(void)
{ {

2
plat/brcm/board/stingray/driver/swreg.c
View file

@ -296,7 +296,7 @@ failed:
return ret; return ret;
} }
/* Update SWREG firmware for all power doman for A2 chip */ /* Update SWREG firmware for all power domain for A2 chip */
int swreg_firmware_update(void) int swreg_firmware_update(void)
{ {
enum sw_reg reg_id; enum sw_reg reg_id;

2
plat/common/aarch64/plat_ehf.c
View file

@ -27,7 +27,7 @@ ehf_pri_desc_t plat_exceptions[] = {
#if SPM_MM #if SPM_MM
EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SP_PRI), EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SP_PRI),
#endif #endif
/* Plaform specific exceptions description */ /* Platform specific exceptions description */
#ifdef PLAT_EHF_DESC #ifdef PLAT_EHF_DESC
PLAT_EHF_DESC, PLAT_EHF_DESC,
#endif #endif

2
plat/imx/common/include/sci/sci_rpc.h
View file

@ -100,7 +100,7 @@ typedef struct sc_rpc_async_msg_s {
void sc_call_rpc(sc_ipc_t ipc, sc_rpc_msg_t *msg, bool no_resp); void sc_call_rpc(sc_ipc_t ipc, sc_rpc_msg_t *msg, bool no_resp);
/*! /*!
* This is an internal function to dispath an RPC call that has * This is an internal function to dispatch an RPC call that has
* arrived via IPC over an MU. It is called by server-side SCFW. * arrived via IPC over an MU. It is called by server-side SCFW.
* *
* @param[in] mu MU message arrived on * @param[in] mu MU message arrived on

4
plat/imx/common/include/sci/svc/pad/sci_pad_api.h
View file

@ -42,7 +42,7 @@
* *
* Pads are managed as a resource by the Resource Manager (RM). They have * Pads are managed as a resource by the Resource Manager (RM). They have
* assigned owners and only the owners can configure the pads. Some of the * assigned owners and only the owners can configure the pads. Some of the
* pads are reserved for use by the SCFW itself and this can be overriden * pads are reserved for use by the SCFW itself and this can be overridden
* with the implementation of board_config_sc(). Additionally, pads may * with the implementation of board_config_sc(). Additionally, pads may
* be assigned to various other partitions via the implementation of * be assigned to various other partitions via the implementation of
* board_system_config(). * board_system_config().
@ -156,7 +156,7 @@ typedef uint8_t sc_pad_config_t;
* This type is used to declare a pad low-power isolation config. * This type is used to declare a pad low-power isolation config.
* ISO_LATE is the most common setting. ISO_EARLY is only used when * ISO_LATE is the most common setting. ISO_EARLY is only used when
* an output pad is directly determined by another input pad. The * an output pad is directly determined by another input pad. The
* other two are only used when SW wants to directly contol isolation. * other two are only used when SW wants to directly control isolation.
*/ */
typedef uint8_t sc_pad_iso_t; typedef uint8_t sc_pad_iso_t;

2
plat/imx/common/include/sci/svc/pm/sci_pm_api.h
View file

@ -294,7 +294,7 @@ sc_err_t sc_pm_get_sys_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
* Note some resources are still not accessible even when powered up if bus * Note some resources are still not accessible even when powered up if bus
* transactions go through a fabric not powered up. Examples of this are * transactions go through a fabric not powered up. Examples of this are
* resources in display and capture subsystems which require the display * resources in display and capture subsystems which require the display
* controller or the imaging subsytem to be powered up first. * controller or the imaging subsystem to be powered up first.
* *
* Not that resources are grouped into power domains by the underlying * Not that resources are grouped into power domains by the underlying
* hardware. If any resource in the domain is on, the entire power domain * hardware. If any resource in the domain is on, the entire power domain

2
plat/imx/imx8m/gpc_common.c
View file

@ -98,7 +98,7 @@ void imx_set_cpu_lpm(unsigned int core_id, bool pdn)
/* assert the pcg pcr bit of the core */ /* assert the pcg pcr bit of the core */
mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);
} else { } else {
/* disbale CORE WFI PDN & IRQ PUP */ /* disable CORE WFI PDN & IRQ PUP */
mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) |
COREx_IRQ_WUP(core_id)); COREx_IRQ_WUP(core_id));
/* deassert the pcg pcr bit of the core */ /* deassert the pcg pcr bit of the core */

2
plat/imx/imx8m/imx8mm/gpc.c
View file

@ -376,7 +376,7 @@ void imx_gpc_init(void)
/* /*
* Set the CORE & SCU power up timing: * Set the CORE & SCU power up timing:
* SW = 0x1, SW2ISO = 0x1; * SW = 0x1, SW2ISO = 0x1;
* the CPU CORE and SCU power up timming counter * the CPU CORE and SCU power up timing counter
* is drived by 32K OSC, each domain's power up * is drived by 32K OSC, each domain's power up
* latency is (SW + SW2ISO) / 32768 * latency is (SW + SW2ISO) / 32768
*/ */

2
plat/imx/imx8m/imx8mn/gpc.c
View file

@ -170,7 +170,7 @@ void imx_gpc_init(void)
/* /*
* Set the CORE & SCU power up timing: * Set the CORE & SCU power up timing:
* SW = 0x1, SW2ISO = 0x1; * SW = 0x1, SW2ISO = 0x1;
* the CPU CORE and SCU power up timming counter * the CPU CORE and SCU power up timing counter
* is drived by 32K OSC, each domain's power up * is drived by 32K OSC, each domain's power up
* latency is (SW + SW2ISO) / 32768 * latency is (SW + SW2ISO) / 32768
*/ */

2
plat/imx/imx8m/imx8mp/gpc.c
View file

@ -337,7 +337,7 @@ void imx_gpc_init(void)
/* /*
* Set the CORE & SCU power up timing: * Set the CORE & SCU power up timing:
* SW = 0x1, SW2ISO = 0x1; * SW = 0x1, SW2ISO = 0x1;
* the CPU CORE and SCU power up timming counter * the CPU CORE and SCU power up timing counter
* is drived by 32K OSC, each domain's power up * is drived by 32K OSC, each domain's power up
* latency is (SW + SW2ISO) / 32768 * latency is (SW + SW2ISO) / 32768
*/ */

2
plat/imx/imx8m/imx8mq/gpc.c
View file

@ -417,7 +417,7 @@ void imx_gpc_init(void)
/* set all mix/PU in A53 domain */ /* set all mix/PU in A53 domain */
mmio_write_32(IMX_GPC_BASE + PGC_CPU_0_1_MAPPING, 0xfffd); mmio_write_32(IMX_GPC_BASE + PGC_CPU_0_1_MAPPING, 0xfffd);
/* set SCU timming */ /* set SCU timing */
mmio_write_32(IMX_GPC_BASE + PGC_SCU_TIMING, mmio_write_32(IMX_GPC_BASE + PGC_SCU_TIMING,
(0x59 << 10) | 0x5B | (0x2 << 20)); (0x59 << 10) | 0x5B | (0x2 << 20));

2
plat/intel/soc/agilex/bl31_plat_setup.c
View file

@ -155,7 +155,7 @@ const mmap_region_t plat_agilex_mmap[] = {
/******************************************************************************* /*******************************************************************************
* Perform the very early platform specific architectural setup here. At the * Perform the very early platform specific architectural setup here. At the
* moment this is only intializes the mmu in a quick and dirty way. * moment this is only initializes the mmu in a quick and dirty way.
******************************************************************************/ ******************************************************************************/
void bl31_plat_arch_setup(void) void bl31_plat_arch_setup(void)
{ {

2
plat/intel/soc/common/sip/socfpga_sip_fcs.c
View file

@ -1804,7 +1804,7 @@ int intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize(uint32_t session_i
/* /*
* Source data must be 4 bytes aligned * Source data must be 4 bytes aligned
* Source addrress must be 8 bytes aligned * Source address must be 8 bytes aligned
* User data must be 8 bytes aligned * User data must be 8 bytes aligned
*/ */
if ((dst_size == NULL) || (mbox_error == NULL) || if ((dst_size == NULL) || (mbox_error == NULL) ||

2
plat/intel/soc/n5x/bl31_plat_setup.c
View file

@ -140,7 +140,7 @@ const mmap_region_t plat_dm_mmap[] = {
/******************************************************************************* /*******************************************************************************
* Perform the very early platform specific architectural setup here. At the * Perform the very early platform specific architectural setup here. At the
* moment this is only intializes the mmu in a quick and dirty way. * moment this is only initializes the mmu in a quick and dirty way.
******************************************************************************/ ******************************************************************************/
void bl31_plat_arch_setup(void) void bl31_plat_arch_setup(void)
{ {

2
plat/intel/soc/stratix10/bl31_plat_setup.c
View file

@ -147,7 +147,7 @@ const mmap_region_t plat_stratix10_mmap[] = {
/******************************************************************************* /*******************************************************************************
* Perform the very early platform specific architectural setup here. At the * Perform the very early platform specific architectural setup here. At the
* moment this is only intializes the mmu in a quick and dirty way. * moment this is only initializes the mmu in a quick and dirty way.
******************************************************************************/ ******************************************************************************/
void bl31_plat_arch_setup(void) void bl31_plat_arch_setup(void)
{ {

2
plat/marvell/armada/a8k/common/plat_pm.c
View file

@ -423,7 +423,7 @@ static int a8k_pwr_domain_on(u_register_t mpidr)
} else } else
#endif #endif
{ {
/* proprietary CPU ON exection flow */ /* proprietary CPU ON execution flow */
plat_marvell_cpu_on(mpidr); plat_marvell_cpu_on(mpidr);
} }
return 0; return 0;

2
plat/marvell/armada/common/marvell_ddr_info.c
View file

@ -34,7 +34,7 @@
DRAM_AREA_LENGTH_MASK) >> DRAM_AREA_LENGTH_OFFS DRAM_AREA_LENGTH_MASK) >> DRAM_AREA_LENGTH_OFFS
/* Mapping between DDR area length and real DDR size is specific and looks like /* Mapping between DDR area length and real DDR size is specific and looks like
* bellow: * below:
* 0 => 384 MB * 0 => 384 MB
* 1 => 768 MB * 1 => 768 MB
* 2 => 1536 MB * 2 => 1536 MB

2
plat/mediatek/include/mtk_sip_svc.h
View file

@ -97,7 +97,7 @@ struct smc_descriptor {
}; };
/* /*
* This function should be implemented in MediaTek SOC directory. It fullfills * This function should be implemented in MediaTek SOC directory. It fulfills
* MTK_SIP_SET_AUTHORIZED_SECURE_REG SiP call by checking the sreg with the * MTK_SIP_SET_AUTHORIZED_SECURE_REG SiP call by checking the sreg with the
* predefined secure register list, if a match was found, set val to sreg. * predefined secure register list, if a match was found, set val to sreg.
* *

2
plat/mediatek/mt8173/bl31_plat_setup.c
View file

@ -129,7 +129,7 @@ void bl31_platform_setup(void)
/******************************************************************************* /*******************************************************************************
* Perform the very early platform specific architectural setup here. At the * Perform the very early platform specific architectural setup here. At the
* moment this is only intializes the mmu in a quick and dirty way. * moment this is only initializes the mmu in a quick and dirty way.
******************************************************************************/ ******************************************************************************/
void bl31_plat_arch_setup(void) void bl31_plat_arch_setup(void)
{ {

2
plat/mediatek/mt8173/drivers/spm/spm.c
View file

@ -20,7 +20,7 @@
* - spm_suspend.c for system power control in system suspend scenario. * - spm_suspend.c for system power control in system suspend scenario.
* *
* This file provide utility functions common to hotplug, mcdi(idle), suspend * This file provide utility functions common to hotplug, mcdi(idle), suspend
* power scenarios. A bakery lock (software lock) is incoporated to protect * power scenarios. A bakery lock (software lock) is incorporated to protect
* certain critical sections to avoid kicking different SPM firmware * certain critical sections to avoid kicking different SPM firmware
* concurrently. * concurrently.
*/ */

2
plat/mediatek/mt8183/bl31_plat_setup.c
View file

@ -163,7 +163,7 @@ void bl31_platform_setup(void)
/******************************************************************************* /*******************************************************************************
* Perform the very early platform specific architectural setup here. At the * Perform the very early platform specific architectural setup here. At the
* moment this is only intializes the mmu in a quick and dirty way. * moment this is only initializes the mmu in a quick and dirty way.
******************************************************************************/ ******************************************************************************/
void bl31_plat_arch_setup(void) void bl31_plat_arch_setup(void)
{ {

2
plat/mediatek/mt8186/bl31_plat_setup.c
View file

@ -102,7 +102,7 @@ void bl31_platform_setup(void)
/******************************************************************************* /*******************************************************************************
* Perform the very early platform specific architectural setup here. At the * Perform the very early platform specific architectural setup here. At the
* moment this is only intializes the mmu in a quick and dirty way. * moment this is only initializes the mmu in a quick and dirty way.
******************************************************************************/ ******************************************************************************/
void bl31_plat_arch_setup(void) void bl31_plat_arch_setup(void)
{ {

2
plat/mediatek/mt8192/bl31_plat_setup.c
View file

@ -110,7 +110,7 @@ void bl31_platform_setup(void)
/******************************************************************************* /*******************************************************************************
* Perform the very early platform specific architectural setup here. At the * Perform the very early platform specific architectural setup here. At the
* moment this is only intializes the mmu in a quick and dirty way. * moment this is only initializes the mmu in a quick and dirty way.
******************************************************************************/ ******************************************************************************/
void bl31_plat_arch_setup(void) void bl31_plat_arch_setup(void)
{ {

2
plat/mediatek/mt8195/bl31_plat_setup.c
View file

@ -106,7 +106,7 @@ void bl31_platform_setup(void)
/******************************************************************************* /*******************************************************************************
* Perform the very early platform specific architectural setup here. At the * Perform the very early platform specific architectural setup here. At the
* moment this is only intializes the mmu in a quick and dirty way. * moment this is only initializes the mmu in a quick and dirty way.
******************************************************************************/ ******************************************************************************/
void bl31_plat_arch_setup(void) void bl31_plat_arch_setup(void)
{ {

8
plat/mediatek/mt8195/drivers/apusys/apupll.c
View file

@ -268,7 +268,7 @@ static int32_t _cal_pll_data(uint32_t *pd, uint32_t *dds, uint32_t freq)
* @pll_idx: Which PLL to enable/disable * @pll_idx: Which PLL to enable/disable
* @on: 1 -> enable, 0 -> disable. * @on: 1 -> enable, 0 -> disable.
* *
* This funciton will only change RG_PLL_EN of CON1 for pll[pll_idx]. * This function will only change RG_PLL_EN of CON1 for pll[pll_idx].
* *
* Context: Any context. * Context: Any context.
*/ */
@ -286,7 +286,7 @@ static void _pll_en(uint32_t pll_idx, bool on)
* @pll_idx: Which PLL to enable/disable * @pll_idx: Which PLL to enable/disable
* @on: 1 -> enable, 0 -> disable. * @on: 1 -> enable, 0 -> disable.
* *
* This funciton will only change PLL_SDM_PWR_ON of CON3 for pll[pll_idx]. * This function will only change PLL_SDM_PWR_ON of CON3 for pll[pll_idx].
* *
* Context: Any context. * Context: Any context.
*/ */
@ -304,7 +304,7 @@ static void _pll_pwr(uint32_t pll_idx, bool on)
* @pll_idx: Which PLL to enable/disable * @pll_idx: Which PLL to enable/disable
* @enable: 1 -> turn on isolation, 0 -> turn off isolation. * @enable: 1 -> turn on isolation, 0 -> turn off isolation.
* *
* This funciton will turn on/off pll isolation by * This function will turn on/off pll isolation by
* changing PLL_SDM_PWR_ON of CON3 for pll[pll_idx]. * changing PLL_SDM_PWR_ON of CON3 for pll[pll_idx].
* *
* Context: Any context. * Context: Any context.
@ -324,7 +324,7 @@ static void _pll_iso(uint32_t pll_idx, bool enable)
* @on: 1 -> enable, 0 -> disable. * @on: 1 -> enable, 0 -> disable.
* @fhctl_en: enable or disable fhctl function * @fhctl_en: enable or disable fhctl function
* *
* This is the entry poing for controlling pll and fhctl funciton on/off. * This is the entry poing for controlling pll and fhctl function on/off.
* Caller can chose only enable pll instead of fhctl function. * Caller can chose only enable pll instead of fhctl function.
* *
* Context: Any context. * Context: Any context.

2
plat/nvidia/tegra/common/tegra_bl31_setup.c
View file

@ -262,7 +262,7 @@ void bl31_plat_runtime_setup(void)
/******************************************************************************* /*******************************************************************************
* Perform the very early platform specific architectural setup here. At the * Perform the very early platform specific architectural setup here. At the
* moment this only intializes the mmu in a quick and dirty way. * moment this only initializes the mmu in a quick and dirty way.
******************************************************************************/ ******************************************************************************/
void bl31_plat_arch_setup(void) void bl31_plat_arch_setup(void)
{ {

2
plat/nvidia/tegra/drivers/memctrl/memctrl_v2.c
View file

@ -301,7 +301,7 @@ void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes)
if (video_mem_base != 0U) { if (video_mem_base != 0U) {
/* /*
* Lock the non overlapping memory being cleared so that * Lock the non overlapping memory being cleared so that
* other masters do not accidently write to it. The memory * other masters do not accidentally write to it. The memory
* would be unlocked once the non overlapping region is * would be unlocked once the non overlapping region is
* cleared and the new memory settings take effect. * cleared and the new memory settings take effect.
*/ */

2
plat/nvidia/tegra/include/drivers/tegra_gic.h
View file

@ -19,7 +19,7 @@ typedef struct pcpu_fiq_state {
} pcpu_fiq_state_t; } pcpu_fiq_state_t;
/******************************************************************************* /*******************************************************************************
* Fucntion declarations * Function declarations
******************************************************************************/ ******************************************************************************/
void tegra_gic_cpuif_deactivate(void); void tegra_gic_cpuif_deactivate(void);
void tegra_gic_init(void); void tegra_gic_init(void);

2
plat/nvidia/tegra/include/t186/tegra_def.h
View file

@ -84,7 +84,7 @@
#define TEGRA_CLK_SE TEGRA186_CLK_SE #define TEGRA_CLK_SE TEGRA186_CLK_SE
/******************************************************************************* /*******************************************************************************
* Tegra Miscellanous register constants * Tegra Miscellaneous register constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_MISC_BASE U(0x00100000) #define TEGRA_MISC_BASE U(0x00100000)
#define HARDWARE_REVISION_OFFSET U(0x4) #define HARDWARE_REVISION_OFFSET U(0x4)

2
plat/nvidia/tegra/include/t194/tegra_def.h
View file

@ -60,7 +60,7 @@
#define TEGRA_CLK_SE TEGRA194_CLK_SE #define TEGRA_CLK_SE TEGRA194_CLK_SE
/******************************************************************************* /*******************************************************************************
* Tegra Miscellanous register constants * Tegra Miscellaneous register constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_MISC_BASE U(0x00100000) #define TEGRA_MISC_BASE U(0x00100000)

2
plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h
View file

@ -40,7 +40,7 @@ typedef enum {
/* index 83 is deprecated */ /* index 83 is deprecated */
TEGRA_ARI_PERFMON = 84U, TEGRA_ARI_PERFMON = 84U,
TEGRA_ARI_UPDATE_CCPLEX_GSC = 85U, TEGRA_ARI_UPDATE_CCPLEX_GSC = 85U,
/* index 86 is depracated */ /* index 86 is deprecated */
/* index 87 is deprecated */ /* index 87 is deprecated */
TEGRA_ARI_ROC_FLUSH_CACHE_ONLY = 88U, TEGRA_ARI_ROC_FLUSH_CACHE_ONLY = 88U,
TEGRA_ARI_ROC_FLUSH_CACHE_TRBITS = 89U, TEGRA_ARI_ROC_FLUSH_CACHE_TRBITS = 89U,

2
plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h
View file

@ -17,7 +17,7 @@
/** /**
* Current version - Major version increments may break backwards * Current version - Major version increments may break backwards
* compatiblity and binary compatibility. Minor version increments * compatibility and binary compatibility. Minor version increments
* occur when there is only new functionality. * occur when there is only new functionality.
*/ */
enum { enum {

2
plat/nvidia/tegra/soc/t194/plat_ras.c
View file

@ -284,7 +284,7 @@ static int32_t tegra194_ras_node_handler(uint32_t errselr, const char *name,
ERROR("RAS Error in %s, ERRSELR_EL1=0x%x:\n", name, errselr); ERROR("RAS Error in %s, ERRSELR_EL1=0x%x:\n", name, errselr);
ERROR("\tStatus = 0x%" PRIx64 "\n", status); ERROR("\tStatus = 0x%" PRIx64 "\n", status);
/* Print uncorrectable errror information. */ /* Print uncorrectable error information. */
if (ERR_STATUS_GET_FIELD(status, UE) != 0U) { if (ERR_STATUS_GET_FIELD(status, UE) != 0U) {
ERR_STATUS_SET_FIELD(val, UE, 1); ERR_STATUS_SET_FIELD(val, UE, 1);

2
plat/nxp/common/setup/ls_bl31_setup.c
View file

@ -174,7 +174,7 @@ void bl31_platform_setup(void)
soc_platform_setup(); soc_platform_setup();
/* Console logs gone missing as part going to /* Console logs gone missing as part going to
* EL1 for initilizing Bl32 if present. * EL1 for initializing Bl32 if present.
* console flush is necessary to avoid it. * console flush is necessary to avoid it.
*/ */
(void)console_flush(); (void)console_flush();

2
plat/nxp/soc-ls1088a/include/soc.h
View file

@ -112,7 +112,7 @@
#define IPSTPCR1_VALUE 0x000003FF #define IPSTPCR1_VALUE 0x000003FF
#define IPSTPCR2_VALUE 0x00013006 #define IPSTPCR2_VALUE 0x00013006
/* Dont' stop UART */ /* Don't stop UART */
#define IPSTPCR3_VALUE 0x0000033A #define IPSTPCR3_VALUE 0x0000033A
#define IPSTPCR4_VALUE 0x00103300 #define IPSTPCR4_VALUE 0x00103300

2
plat/qti/common/src/qti_bl31_setup.c
View file

@ -81,7 +81,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
/******************************************************************************* /*******************************************************************************
* Perform the very early platform specific architectural setup here. At the * Perform the very early platform specific architectural setup here. At the
* moment this only intializes the mmu in a quick and dirty way. * moment this only initializes the mmu in a quick and dirty way.
******************************************************************************/ ******************************************************************************/
void bl31_plat_arch_setup(void) void bl31_plat_arch_setup(void)
{ {

2
plat/renesas/rcar/bl2_plat_setup.c
View file

@ -1190,7 +1190,7 @@ static void bl2_init_generic_timer(void)
break; break;
} }
#endif /* RCAR_LSI == RCAR_E3 */ #endif /* RCAR_LSI == RCAR_E3 */
/* Update memory mapped and register based freqency */ /* Update memory mapped and register based frequency */
write_cntfrq_el0((u_register_t )reg_cntfid); write_cntfrq_el0((u_register_t )reg_cntfid);
mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid); mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid);
/* Enable counter */ /* Enable counter */

2
plat/rockchip/common/bl31_plat_setup.c
View file

@ -87,7 +87,7 @@ void bl31_platform_setup(void)
/******************************************************************************* /*******************************************************************************
* Perform the very early platform specific architectural setup here. At the * Perform the very early platform specific architectural setup here. At the
* moment this is only intializes the mmu in a quick and dirty way. * moment this is only initializes the mmu in a quick and dirty way.
******************************************************************************/ ******************************************************************************/
void bl31_plat_arch_setup(void) void bl31_plat_arch_setup(void)
{ {

2
plat/rockchip/common/drivers/pmu/pmu_com.h
View file

@ -90,7 +90,7 @@ static int check_cpu_wfie(uint32_t cpu_id, uint32_t wfie_msk)
/* /*
* wfe/wfi tracking not possible, hopefully the host * wfe/wfi tracking not possible, hopefully the host
* was sucessful in enabling wfe/wfi. * was successful in enabling wfe/wfi.
* We'll give a bit of additional time, like the kernel does. * We'll give a bit of additional time, like the kernel does.
*/ */
if ((cluster_id && clstb_cpu_wfe < 0) || if ((cluster_id && clstb_cpu_wfe < 0) ||

2
plat/rockchip/common/sp_min_plat_setup.c
View file

@ -82,7 +82,7 @@ void sp_min_platform_setup(void)
/******************************************************************************* /*******************************************************************************
* Perform the very early platform specific architectural setup here. At the * Perform the very early platform specific architectural setup here. At the
* moment this is only intializes the mmu in a quick and dirty way. * moment this is only initializes the mmu in a quick and dirty way.
******************************************************************************/ ******************************************************************************/
void sp_min_plat_arch_setup(void) void sp_min_plat_arch_setup(void)
{ {

2
plat/rockchip/rk3288/drivers/pmu/pmu.c
View file

@ -288,7 +288,7 @@ int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, uint64_t entrypoint)
/* /*
* We communicate with the bootrom to active the cpus other * We communicate with the bootrom to active the cpus other
* than cpu0, after a blob of initialize code, they will * than cpu0, after a blob of initialize code, they will
* stay at wfe state, once they are actived, they will check * stay at wfe state, once they are activated, they will check
* the mailbox: * the mailbox:
* sram_base_addr + 4: 0xdeadbeaf * sram_base_addr + 4: 0xdeadbeaf
* sram_base_addr + 8: start address for pc * sram_base_addr + 8: start address for pc

2
plat/rockchip/rk3288/drivers/soc/soc.c
View file

@ -216,7 +216,7 @@ void __dead2 rockchip_soc_soft_reset(void)
/* /*
* Maybe the HW needs some times to reset the system, * Maybe the HW needs some times to reset the system,
* so we do not hope the core to excute valid codes. * so we do not hope the core to execute valid codes.
*/ */
while (1) while (1)
; ;

6
plat/rockchip/rk3328/drivers/pmu/pmu.c
View file

@ -202,7 +202,7 @@ void __dead2 rockchip_soc_soft_reset(void)
dsb(); dsb();
/* /*
* Maybe the HW needs some times to reset the system, * Maybe the HW needs some times to reset the system,
* so we do not hope the core to excute valid codes. * so we do not hope the core to execute valid codes.
*/ */
while (1) while (1)
; ;
@ -210,7 +210,7 @@ void __dead2 rockchip_soc_soft_reset(void)
/* /*
* For PMIC RK805, its sleep pin is connect with gpio2_d2 from rk3328. * For PMIC RK805, its sleep pin is connect with gpio2_d2 from rk3328.
* If the PMIC is configed for responding the sleep pin to power off it, * If the PMIC is configured for responding the sleep pin to power off it,
* once the pin is output high, it will get the pmic power off. * once the pin is output high, it will get the pmic power off.
*/ */
void __dead2 rockchip_soc_system_off(void) void __dead2 rockchip_soc_system_off(void)
@ -462,7 +462,7 @@ static __sramfunc void sram_udelay(uint32_t us)
/* /*
* For PMIC RK805, its sleep pin is connect with gpio2_d2 from rk3328. * For PMIC RK805, its sleep pin is connect with gpio2_d2 from rk3328.
* If the PMIC is configed for responding the sleep pin * If the PMIC is configured for responding the sleep pin
* to get it into sleep mode, * to get it into sleep mode,
* once the pin is output high, it will get the pmic into sleep mode. * once the pin is output high, it will get the pmic into sleep mode.
*/ */

2
plat/rockchip/rk3328/drivers/soc/soc.h
View file

@ -27,7 +27,7 @@ enum plls_id {
DPLL_ID, DPLL_ID,
CPLL_ID, CPLL_ID,
GPLL_ID, GPLL_ID,
REVERVE, RESERVE,
NPLL_ID, NPLL_ID,
MAX_PLL, MAX_PLL,
}; };

2
plat/rockchip/rk3368/drivers/soc/soc.c
View file

@ -202,7 +202,7 @@ void __dead2 rockchip_soc_soft_reset(void)
/* /*
* Maybe the HW needs some times to reset the system, * Maybe the HW needs some times to reset the system,
* so we do not hope the core to excute valid codes. * so we do not hope the core to execute valid codes.
*/ */
while (1) while (1)
; ;

2
plat/rockchip/rk3399/drivers/dram/dfs.c
View file

@ -1696,7 +1696,7 @@ static int to_get_clk_index(unsigned int mhz)
pll_cnt = ARRAY_SIZE(dpll_rates_table); pll_cnt = ARRAY_SIZE(dpll_rates_table);
/* Assumming rate_table is in descending order */ /* Assuming rate_table is in descending order */
for (i = 0; i < pll_cnt; i++) { for (i = 0; i < pll_cnt; i++) {
if (mhz >= dpll_rates_table[i].mhz) if (mhz >= dpll_rates_table[i].mhz)
break; break;

2
plat/rockchip/rk3399/drivers/dram/dram_spec_timing.h
View file

@ -103,7 +103,7 @@ struct dram_timing_t {
uint32_t tcksre; uint32_t tcksre;
uint32_t tcksrx; uint32_t tcksrx;
uint32_t tdpd; uint32_t tdpd;
/* mode regiter timing */ /* mode register timing */
uint32_t tmod; uint32_t tmod;
uint32_t tmrd; uint32_t tmrd;
uint32_t tmrr; uint32_t tmrr;

2
plat/rockchip/rk3399/drivers/dram/suspend.c
View file

@ -561,7 +561,7 @@ static __pmusramfunc int dram_switch_to_next_index(
ch_count = sdram_params->num_channels; ch_count = sdram_params->num_channels;
/* LPDDR4 f2 cann't do training, all training will fail */ /* LPDDR4 f2 can't do training, all training will fail */
for (ch = 0; ch < ch_count; ch++) { for (ch = 0; ch < ch_count; ch++) {
/* /*
* Without this disabled for LPDDR4 we end up writing 0's * Without this disabled for LPDDR4 we end up writing 0's

2
plat/rockchip/rk3399/drivers/gpio/rk3399_gpio.c
View file

@ -376,7 +376,7 @@ void plat_rockchip_restore_gpio(void)
mmio_write_32(base + SWPORTA_DDR, save->swporta_ddr); mmio_write_32(base + SWPORTA_DDR, save->swporta_ddr);
mmio_write_32(base + INTEN, save->inten); mmio_write_32(base + INTEN, save->inten);
mmio_write_32(base + INTMASK, save->intmask); mmio_write_32(base + INTMASK, save->intmask);
mmio_write_32(base + INTTYPE_LEVEL, save->inttype_level), mmio_write_32(base + INTTYPE_LEVEL, save->inttype_level);
mmio_write_32(base + INT_POLARITY, save->int_polarity); mmio_write_32(base + INT_POLARITY, save->int_polarity);
mmio_write_32(base + DEBOUNCE, save->debounce); mmio_write_32(base + DEBOUNCE, save->debounce);
mmio_write_32(base + LS_SYNC, save->ls_sync); mmio_write_32(base + LS_SYNC, save->ls_sync);

2
plat/rockchip/rk3399/drivers/m0/src/suspend.c
View file

@ -30,7 +30,7 @@ __attribute__((noreturn)) void m0_main(void)
} }
/* /*
* FSM power secquence is .. -> ST_INPUT_CLAMP(step.17) -> .. -> * FSM power sequence is .. -> ST_INPUT_CLAMP(step.17) -> .. ->
* ST_WAKEUP_RESET -> ST_EXT_PWRUP-> ST_RELEASE_CLAMP -> * ST_WAKEUP_RESET -> ST_EXT_PWRUP-> ST_RELEASE_CLAMP ->
* ST_24M_OSC_EN -> .. -> ST_WAKEUP_RESET_CLR(step.26) -> .., * ST_24M_OSC_EN -> .. -> ST_WAKEUP_RESET_CLR(step.26) -> ..,
* INPUT_CLAMP and WAKEUP_RESET will hold the SOC not affect by * INPUT_CLAMP and WAKEUP_RESET will hold the SOC not affect by

2
plat/rockchip/rk3399/drivers/secure/secure.h
View file

@ -32,7 +32,7 @@
/* security config pmu slave ip */ /* security config pmu slave ip */
/* All of slaves is ns */ /* All of slaves is ns */
#define SGRF_PMU_SLV_S_NS BIT_WITH_WMSK(0) #define SGRF_PMU_SLV_S_NS BIT_WITH_WMSK(0)
/* slaves secure attr is configed */ /* slaves secure attr is configured */
#define SGRF_PMU_SLV_S_CFGED WMSK_BIT(0) #define SGRF_PMU_SLV_S_CFGED WMSK_BIT(0)
#define SGRF_PMU_SLV_CRYPTO1_NS WMSK_BIT(1) #define SGRF_PMU_SLV_CRYPTO1_NS WMSK_BIT(1)

2
plat/rockchip/rk3399/drivers/soc/soc.c
View file

@ -343,7 +343,7 @@ void __dead2 soc_global_soft_reset(void)
/* /*
* Maybe the HW needs some times to reset the system, * Maybe the HW needs some times to reset the system,
* so we do not hope the core to excute valid codes. * so we do not hope the core to execute valid codes.
*/ */
while (1) while (1)
; ;

2
plat/rpi/rpi4/rpi4_pci_svc.c
View file

@ -11,7 +11,7 @@
* it. Given that it's not ECAM compliant yet reasonably simple, it makes for * it. Given that it's not ECAM compliant yet reasonably simple, it makes for
* an excellent example of the PCI SMCCC interface. * an excellent example of the PCI SMCCC interface.
* *
* The PCI SMCCC interface is described in DEN0115 availabe from: * The PCI SMCCC interface is described in DEN0115 available from:
* https://developer.arm.com/documentation/den0115/latest * https://developer.arm.com/documentation/den0115/latest
*/ */

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