Djam/arm-trusted-firmware
1
0
Fork 0
mirror of https://github.com/ARM-software/arm-trusted-firmware.git synced 2025-04-16 09:34:18 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

fix(errata): workaround for Cortex-A78C erratum 2395411

Browse source 
Cortex-A78C erratum 2395411 is a Cat B erratum that affects
revisions r0p1 and r0p2, and is currently open. The workaround
is to set CPUACTLR2_EL1[40] to 1, which will disable folding
of demand requests into older prefetches with L2 miss requests
outstanding.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN2004089/latest

Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com>
Change-Id: I4f0fb278ac20a2eb4dd7e4efd1b1246dd85e48c4
This commit is contained in:
Akram Ahmad 2022-07-19 14:38:46 +01:00
parent 1631f9c75c
commit 4b6f0026ea
4 changed files with 58 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
docs/design/cpu-specific-build-macros.rst
View file

@ -335,6 +335,10 @@ For Cortex-A78C, the following errata build flags are defined :
Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and
it is still open.
- ``ERRATA_A78C_2395411`` : This applies errata 2395411 workaround to
Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This
erratum is still open.
For Cortex-X1 CPU, the following errata build flags are defined:
- ``ERRATA_X1_1821534`` : This applies errata 1821534 workaround to Cortex-X1

10
include/lib/cpus/aarch64/cortex_a78c.h
View file

@ -13,12 +13,18 @@
/* Cortex-A76 loop count for CVE-2022-23960 mitigation */
#define CORTEX_A78C_BHB_LOOP_COUNT U(32)
/*******************************************************************************
* CPU Auxiliary Control register 2 specific definitions.
* ****************************************************************************/
#define CORTEX_A78C_CPUACTLR2_EL1 S3_0_C15_C1_1
#define CORTEX_A78C_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40)
/*******************************************************************************
* CPU Extended Control register specific definitions.
******************************************************************************/
#define CORTEX_A78C_CPUECTLR_EL1 S3_0_C15_C1_4
#define CORTEX_A78C_CPUECTLR_EL1_BIT6 (ULL(1) << 6)
#define CORTEX_A78C_CPUECTLR_EL1_BIT7 (ULL(1) << 7)
#define CORTEX_A78C_CPUECTLR_EL1_BIT_6 (ULL(1) << 6)
#define CORTEX_A78C_CPUECTLR_EL1_BIT_7 (ULL(1) << 7)
/*******************************************************************************
* CPU Power Control register specific definitions

40
lib/cpus/aarch64/cortex_a78c.S
View file

@ -17,6 +17,36 @@
#error "cortex_a78c must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
/* --------------------------------------------------
* Errata Workaround for Cortex A78C Erratum 2395411.
* This applies to revision r0p1 and r0p2 of the A78C
* and is currently open. It is a Cat B erratum.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x4, x17
* --------------------------------------------------
*/
func errata_a78c_2395411_wa
/* Check revision. */
mov x17, x30
bl check_errata_2395411
cbz x0, 1f
/* Set CPUACTRL2_EL1[40] to 1. */
mrs x1, CORTEX_A78C_CPUACTLR2_EL1
orr x1, x1, #CORTEX_A78C_CPUACTLR2_EL1_BIT_40
msr CORTEX_A78C_CPUACTLR2_EL1, x1
1:
ret x17
endfunc errata_a78c_2395411_wa
func check_errata_2395411
/* Applies to r0p1 and r0p2 */
mov x1, #0x01
mov x2, #0x02
b cpu_rev_var_range
endfunc check_errata_2395411
#if WORKAROUND_CVE_2022_23960
wa_cve_2022_23960_bhb_vector_table CORTEX_A78C_BHB_LOOP_COUNT, cortex_a78c
#endif /* WORKAROUND_CVE_2022_23960 */
@ -43,8 +73,8 @@ func errata_a78c_2132064_wa
* --------------------------------------------------------
*/
mrs x0, CORTEX_A78C_CPUECTLR_EL1
orr x0, x0, #CORTEX_A78C_CPUECTLR_EL1_BIT6
orr x0, x0, #CORTEX_A78C_CPUECTLR_EL1_BIT7
orr x0, x0, #CORTEX_A78C_CPUECTLR_EL1_BIT_6
orr x0, x0, #CORTEX_A78C_CPUECTLR_EL1_BIT_7
msr CORTEX_A78C_CPUECTLR_EL1, x0
isb
1:
@ -121,6 +151,11 @@ func cortex_a78c_reset_func
bl errata_a78c_2242638_wa
#endif
#if ERRATA_A78C_2395411
mov x0, x18
bl errata_a78c_2395411_wa
#endif
#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
/*
* The Cortex-A78c generic vectors are overridden to apply errata
@ -166,6 +201,7 @@ func cortex_a78c_errata_report
*/
report_errata ERRATA_A78C_2132064, cortex_a78c, 2132064
report_errata ERRATA_A78C_2242638, cortex_a78c, 2242638
report_errata ERRATA_A78C_2395411, cortex_a78c, 2395411
report_errata WORKAROUND_CVE_2022_23960, cortex_a78c, cve_2022_23960
ldp x8, x30, [sp], #16

8
lib/cpus/cpu-ops.mk
View file

@ -369,6 +369,10 @@ ERRATA_A78C_2132064 ?=0
# to revisions r0p1 and r0p2 of the A78C cpu. It is still open.
ERRATA_A78C_2242638 ?=0
# Flag to apply erratum 2395411 workaround during reset. This erratum applies
# to revisions r0p1 and r0p2 of the A78C cpu. It is still open.
ERRATA_A78C_2395411 ?=0
# Flag to apply erratum 1821534 workaround during reset. This erratum applies
# to revisions r0p0 - r1p0 of the X1 cpu and fixed in r1p1.
ERRATA_X1_1821534 ?=0
@ -939,6 +943,10 @@ $(eval $(call add_define,ERRATA_A78C_2132064))
$(eval $(call assert_boolean,ERRATA_A78C_2242638))
$(eval $(call add_define,ERRATA_A78C_2242638))
# Process ERRATA_A78C_2395411 flag
$(eval $(call assert_boolean,ERRATA_A78C_2395411))
$(eval $(call add_define,ERRATA_A78C_2395411))
# Process ERRATA_X1_1821534 flag
$(eval $(call assert_boolean,ERRATA_X1_1821534))
$(eval $(call add_define,ERRATA_X1_1821534))