diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index ee86b7e95..6c31d9d4b 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -1435,18 +1435,23 @@ #define HFGWTR_EL2_INIT_VAL ULL(0xC4000000000000) /******************************************************************************* - * FEAT_TCR2 - Extended Translation Control Register + * FEAT_TCR2 - Extended Translation Control Registers ******************************************************************************/ +#define TCR2_EL1 S3_0_C2_C0_3 #define TCR2_EL2 S3_4_C2_C0_3 /******************************************************************************* - * Permission indirection and overlay + * Permission indirection and overlay Registers ******************************************************************************/ +#define PIRE0_EL1 S3_0_C10_C2_2 #define PIRE0_EL2 S3_4_C10_C2_2 +#define PIR_EL1 S3_0_C10_C2_3 #define PIR_EL2 S3_4_C10_C2_3 +#define POR_EL1 S3_0_C10_C2_4 #define POR_EL2 S3_4_C10_C2_4 #define S2PIR_EL2 S3_4_C10_C2_5 +#define S2POR_EL1 S3_0_C10_C2_5 /******************************************************************************* * FEAT_GCS - Guarded Control Stack Registers diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h index 6356cab12..da7b16279 100644 --- a/include/arch/aarch64/arch_helpers.h +++ b/include/arch/aarch64/arch_helpers.h @@ -284,6 +284,7 @@ DEFINE_SYSREG_RW_FUNCS(elr_el1) DEFINE_SYSREG_RW_FUNCS(elr_el2) DEFINE_SYSREG_RW_FUNCS(elr_el3) DEFINE_SYSREG_RW_FUNCS(mdccsr_el0) +DEFINE_SYSREG_RW_FUNCS(mdccint_el1) DEFINE_SYSREG_RW_FUNCS(dbgdtrrx_el0) DEFINE_SYSREG_RW_FUNCS(dbgdtrtx_el0) DEFINE_SYSREG_RW_FUNCS(sp_el1) @@ -504,6 +505,7 @@ DEFINE_RENAME_SYSREG_RW_FUNCS(ich_vmcr_el2, ICH_VMCR_EL2) DEFINE_SYSREG_READ_FUNC(isr_el1) +DEFINE_SYSREG_RW_FUNCS(mdscr_el1) DEFINE_SYSREG_RW_FUNCS(mdcr_el2) DEFINE_SYSREG_RW_FUNCS(mdcr_el3) DEFINE_SYSREG_RW_FUNCS(hstr_el2) @@ -576,6 +578,7 @@ DEFINE_RENAME_SYSREG_RW_FUNCS(ttbr1_el2, TTBR1_EL2) DEFINE_RENAME_IDREG_READ_FUNC(id_aa64mmfr2_el1, ID_AA64MMFR2_EL1) /* Armv8.2 RAS Registers */ +DEFINE_RENAME_SYSREG_RW_FUNCS(disr_el1, DISR_EL1) DEFINE_RENAME_SYSREG_RW_FUNCS(vdisr_el2, VDISR_EL2) DEFINE_RENAME_SYSREG_RW_FUNCS(vsesr_el2, VSESR_EL2) @@ -634,15 +637,20 @@ DEFINE_RENAME_SYSREG_RW_FUNCS(hcrx_el2, HCRX_EL2) DEFINE_RENAME_IDREG_READ_FUNC(id_aa64mmfr3_el1, ID_AA64MMFR3_EL1) /* FEAT_TCR2 Register */ +DEFINE_RENAME_SYSREG_RW_FUNCS(tcr2_el1, TCR2_EL1) DEFINE_RENAME_SYSREG_RW_FUNCS(tcr2_el2, TCR2_EL2) /* FEAT_SxPIE Registers */ +DEFINE_RENAME_SYSREG_RW_FUNCS(pire0_el1, PIRE0_EL1) DEFINE_RENAME_SYSREG_RW_FUNCS(pire0_el2, PIRE0_EL2) +DEFINE_RENAME_SYSREG_RW_FUNCS(pir_el1, PIR_EL1) DEFINE_RENAME_SYSREG_RW_FUNCS(pir_el2, PIR_EL2) DEFINE_RENAME_SYSREG_RW_FUNCS(s2pir_el2, S2PIR_EL2) /* FEAT_SxPOE Registers */ +DEFINE_RENAME_SYSREG_RW_FUNCS(por_el1, POR_EL1) DEFINE_RENAME_SYSREG_RW_FUNCS(por_el2, POR_EL2) +DEFINE_RENAME_SYSREG_RW_FUNCS(s2por_el1, S2POR_EL1) /* FEAT_GCS Registers */ DEFINE_RENAME_SYSREG_RW_FUNCS(gcscr_el2, GCSCR_EL2) diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h index fbaa008f1..74790d1cf 100644 --- a/include/lib/el3_runtime/aarch64/context.h +++ b/include/lib/el3_runtime/aarch64/context.h @@ -109,21 +109,25 @@ #define CTX_AFSR1_EL1 U(0x98) #define CTX_CONTEXTIDR_EL1 U(0xa0) #define CTX_VBAR_EL1 U(0xa8) +#define CTX_MDCCINT_EL1 U(0xb0) +#define CTX_MDSCR_EL1 U(0xb8) + +#define CTX_AARCH64_END U(0xc0) /* Align to the next 16 byte boundary */ /* * If the platform is AArch64-only, there is no need to save and restore these * AArch32 registers. */ #if CTX_INCLUDE_AARCH32_REGS -#define CTX_SPSR_ABT U(0xb0) /* Align to the next 16 byte boundary */ -#define CTX_SPSR_UND U(0xb8) -#define CTX_SPSR_IRQ U(0xc0) -#define CTX_SPSR_FIQ U(0xc8) -#define CTX_DACR32_EL2 U(0xd0) -#define CTX_IFSR32_EL2 U(0xd8) -#define CTX_AARCH32_END U(0xe0) /* Align to the next 16 byte boundary */ +#define CTX_SPSR_ABT (CTX_AARCH64_END + U(0x0)) +#define CTX_SPSR_UND (CTX_AARCH64_END + U(0x8)) +#define CTX_SPSR_IRQ (CTX_AARCH64_END + U(0x10)) +#define CTX_SPSR_FIQ (CTX_AARCH64_END + U(0x18)) +#define CTX_DACR32_EL2 (CTX_AARCH64_END + U(0x20)) +#define CTX_IFSR32_EL2 (CTX_AARCH64_END + U(0x28)) +#define CTX_AARCH32_END (CTX_AARCH64_END + U(0x30)) /* Align to the next 16 byte boundary */ #else -#define CTX_AARCH32_END U(0xb0) /* Align to the next 16 byte boundary */ +#define CTX_AARCH32_END CTX_AARCH64_END #endif /* CTX_INCLUDE_AARCH32_REGS */ /* @@ -146,17 +150,51 @@ #define CTX_TFSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x8)) #define CTX_RGSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x10)) #define CTX_GCR_EL1 (CTX_TIMER_SYSREGS_END + U(0x18)) - -/* Align to the next 16 byte boundary */ -#define CTX_MTE_REGS_END (CTX_TIMER_SYSREGS_END + U(0x20)) +#define CTX_MTE_REGS_END (CTX_TIMER_SYSREGS_END + U(0x20)) /* Align to the next 16 byte boundary */ #else #define CTX_MTE_REGS_END CTX_TIMER_SYSREGS_END #endif /* ENABLE_FEAT_MTE2 */ +#if ENABLE_FEAT_RAS +#define CTX_DISR_EL1 (CTX_MTE_REGS_END + U(0x0)) +#define CTX_RAS_REGS_END (CTX_MTE_REGS_END + U(0x10)) /* Align to the next 16 byte boundary */ +#else +#define CTX_RAS_REGS_END CTX_MTE_REGS_END +#endif /* ENABLE_FEAT_RAS */ + +#if ENABLE_FEAT_S1PIE +#define CTX_PIRE0_EL1 (CTX_RAS_REGS_END + U(0x0)) +#define CTX_PIR_EL1 (CTX_RAS_REGS_END + U(0x8)) +#define CTX_S1PIE_REGS_END (CTX_RAS_REGS_END + U(0x10)) /* Align to the next 16 byte boundary */ +#else +#define CTX_S1PIE_REGS_END CTX_RAS_REGS_END +#endif /* ENABLE_FEAT_S1PIE */ + +#if ENABLE_FEAT_S1POE +#define CTX_POR_EL1 (CTX_S1PIE_REGS_END + U(0x0)) +#define CTX_S1POE_REGS_END (CTX_S1PIE_REGS_END + U(0x10)) /* Align to the next 16 byte boundary */ +#else +#define CTX_S1POE_REGS_END CTX_S1PIE_REGS_END +#endif /* ENABLE_FEAT_S1POE */ + +#if ENABLE_FEAT_S2POE +#define CTX_S2POR_EL1 (CTX_S1POE_REGS_END + U(0x0)) +#define CTX_S2POE_REGS_END (CTX_S1POE_REGS_END + U(0x10)) /* Align to the next 16 byte boundary */ +#else +#define CTX_S2POE_REGS_END CTX_S1POE_REGS_END +#endif /* ENABLE_FEAT_S2POE */ + +#if ENABLE_FEAT_TCR2 +#define CTX_TCR2_EL1 (CTX_S2POE_REGS_END + U(0x0)) +#define CTX_TCR2_REGS_END (CTX_S2POE_REGS_END + U(0x10)) /* Align to the next 16 byte boundary */ +#else +#define CTX_TCR2_REGS_END CTX_S2POE_REGS_END +#endif /* ENABLE_FEAT_TCR2 */ + /* * End of system registers. */ -#define CTX_EL1_SYSREGS_END CTX_MTE_REGS_END +#define CTX_EL1_SYSREGS_END CTX_TCR2_REGS_END /******************************************************************************* * Constants that allow assembler code to access members of and the 'fp_regs' diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index 132b6019f..39f39476f 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -1490,6 +1490,8 @@ static void el1_sysregs_context_save(el1_sysregs_t *ctx) write_ctx_reg(ctx, CTX_AFSR1_EL1, read_afsr1_el1()); write_ctx_reg(ctx, CTX_CONTEXTIDR_EL1, read_contextidr_el1()); write_ctx_reg(ctx, CTX_VBAR_EL1, read_vbar_el1()); + write_ctx_reg(ctx, CTX_MDCCINT_EL1, read_mdccint_el1()); + write_ctx_reg(ctx, CTX_MDSCR_EL1, read_mdscr_el1()); #if CTX_INCLUDE_AARCH32_REGS write_ctx_reg(ctx, CTX_SPSR_ABT, read_spsr_abt()); @@ -1515,6 +1517,36 @@ static void el1_sysregs_context_save(el1_sysregs_t *ctx) write_ctx_reg(ctx, CTX_GCR_EL1, read_gcr_el1()); #endif /* ENABLE_FEAT_MTE2 */ +#if ENABLE_FEAT_RAS + if (is_feat_ras_supported()) { + write_ctx_reg(ctx, CTX_DISR_EL1, read_disr_el1()); + } +#endif + +#if ENABLE_FEAT_S1PIE + if (is_feat_s1pie_supported()) { + write_ctx_reg(ctx, CTX_PIRE0_EL1, read_pire0_el1()); + write_ctx_reg(ctx, CTX_PIR_EL1, read_pir_el1()); + } +#endif + +#if ENABLE_FEAT_S1POE + if (is_feat_s1poe_supported()) { + write_ctx_reg(ctx, CTX_POR_EL1, read_por_el1()); + } +#endif + +#if ENABLE_FEAT_S2POE + if (is_feat_s2poe_supported()) { + write_ctx_reg(ctx, CTX_S2POR_EL1, read_s2por_el1()); + } +#endif + +#if ENABLE_FEAT_TCR2 + if (is_feat_tcr2_supported()) { + write_ctx_reg(ctx, CTX_TCR2_EL1, read_tcr2_el1()); + } +#endif } static void el1_sysregs_context_restore(el1_sysregs_t *ctx) @@ -1545,6 +1577,8 @@ static void el1_sysregs_context_restore(el1_sysregs_t *ctx) write_afsr1_el1(read_ctx_reg(ctx, CTX_AFSR1_EL1)); write_contextidr_el1(read_ctx_reg(ctx, CTX_CONTEXTIDR_EL1)); write_vbar_el1(read_ctx_reg(ctx, CTX_VBAR_EL1)); + write_mdccint_el1(read_ctx_reg(ctx, CTX_MDCCINT_EL1)); + write_mdscr_el1(read_ctx_reg(ctx, CTX_MDSCR_EL1)); #if CTX_INCLUDE_AARCH32_REGS write_spsr_abt(read_ctx_reg(ctx, CTX_SPSR_ABT)); @@ -1570,6 +1604,36 @@ static void el1_sysregs_context_restore(el1_sysregs_t *ctx) write_gcr_el1(read_ctx_reg(ctx, CTX_GCR_EL1)); #endif /* ENABLE_FEAT_MTE2 */ +#if ENABLE_FEAT_RAS + if (is_feat_ras_supported()) { + write_disr_el1(read_ctx_reg(ctx, CTX_DISR_EL1)); + } +#endif + +#if ENABLE_FEAT_S1PIE + if (is_feat_s1pie_supported()) { + write_pire0_el1(read_ctx_reg(ctx, CTX_PIRE0_EL1)); + write_pir_el1(read_ctx_reg(ctx, CTX_PIR_EL1)); + } +#endif + +#if ENABLE_FEAT_S1POE + if (is_feat_s1poe_supported()) { + write_por_el1(read_ctx_reg(ctx, CTX_POR_EL1)); + } +#endif + +#if ENABLE_FEAT_S2POE + if (is_feat_s2poe_supported()) { + write_s2por_el1(read_ctx_reg(ctx, CTX_S2POR_EL1)); + } +#endif + +#if ENABLE_FEAT_TCR2 + if (is_feat_tcr2_supported()) { + write_tcr2_el1(read_ctx_reg(ctx, CTX_TCR2_EL1)); + } +#endif } /*******************************************************************************