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Merge changes from topic "st_uart_update" into integration

Browse source 
* changes:
  feat(st): protect UART during platform init
  feat(stm32mp1): update console management for SP_min
  refactor(stm32mp1): improve console management in BL2
  feat(plat/st): add a function to configure console
  feat(stm32mp1): add stm32_get_boot_interface function
  refactor(stm32mp1): move stm32_save_boot_interface()
  fix(stm32mp1): deconfigure UART RX pins
  feat(stm32_gpio): add a function to reset a pin
  refactor(stm32mp1): sort compilation flags
  feat(stm32mp1): add sign-compare warning
This commit is contained in:
Madhukar Pappireddy 2021-12-14 18:25:39 +01:00 • committed by TrustedFirmware Code Review
commit 4abb0db11b
11 changed files with 238 additions and 144 deletions
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9
drivers/st/gpio/stm32_gpio.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2020, STMicroelectronics - All Rights Reserved
* Copyright (c) 2016-2021, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -283,3 +283,10 @@ void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure)
stm32mp_clk_disable(clock);
}
void set_gpio_reset_cfg(uint32_t bank, uint32_t pin)
{
set_gpio(bank, pin, GPIO_MODE_ANALOG, GPIO_SPEED_LOW,
GPIO_NO_PULL, GPIO_ALTERNATE_(0), DT_DISABLED);
set_gpio_secure_cfg(bank, pin, stm32_gpio_is_secure_at_reset(bank));
}

3
include/drivers/st/stm32_gpio.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2019, STMicroelectronics - All Rights Reserved
* Copyright (c) 2015-2021, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -52,6 +52,7 @@ int dt_set_pinctrl_config(int node);
void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed,
uint32_t pull, uint32_t alternate, uint8_t status);
void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure);
void set_gpio_reset_cfg(uint32_t bank, uint32_t pin);
#endif /*__ASSEMBLER__*/
#endif /* STM32_GPIO_H */

10
plat/st/common/include/stm32mp_common.h
View file

@ -48,11 +48,14 @@ uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst);
uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags);
#endif
#if STM32MP_UART_PROGRAMMER
#if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2)
/* Get the UART address from its instance number */
uintptr_t get_uart_address(uint32_t instance_nb);
#endif
/* Setup the UART console */
int stm32mp_uart_console_setup(void);
/*
* Platform util functions for the GPIO driver
* @bank: Target GPIO bank ID as per DT bindings
@ -69,6 +72,7 @@ uintptr_t get_uart_address(uint32_t instance_nb);
uintptr_t stm32_get_gpio_bank_base(unsigned int bank);
unsigned long stm32_get_gpio_bank_clock(unsigned int bank);
uint32_t stm32_get_gpio_bank_offset(unsigned int bank);
bool stm32_gpio_is_secure_at_reset(unsigned int bank);
/* Return node offset for target GPIO bank ID @bank or a FDT error code */
int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank);
@ -114,4 +118,8 @@ int stm32mp_check_header(boot_api_image_header_t *header, uintptr_t buffer);
int stm32mp_map_ddr_non_cacheable(void);
int stm32mp_unmap_ddr(void);
/* Functions to save and get boot peripheral info */
void stm32_save_boot_interface(uint32_t interface, uint32_t instance);
void stm32_get_boot_interface(uint32_t *interface, uint32_t *instance);
#endif /* STM32MP_COMMON_H */

87
plat/st/common/stm32mp_common.c
View file

@ -7,17 +7,23 @@
#include <assert.h>
#include <errno.h>
#include <platform_def.h>
#include <arch_helpers.h>
#include <common/debug.h>
#include <drivers/delay_timer.h>
#include <drivers/st/stm32_console.h>
#include <drivers/st/stm32mp_clkfunc.h>
#include <drivers/st/stm32mp_reset.h>
#include <lib/smccc.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
#include <services/arm_arch_svc.h>
#include <platform_def.h>
#define HEADER_VERSION_MAJOR_MASK GENMASK(23, 16)
#define RESET_TIMEOUT_US_1MS 1000U
static console_t console;
uintptr_t plat_get_ns_image_entrypoint(void)
{
@ -128,6 +134,83 @@ int stm32mp_unmap_ddr(void)
STM32MP_DDR_MAX_SIZE);
}
#if defined(IMAGE_BL2)
static void reset_uart(uint32_t reset)
{
int ret;
ret = stm32mp_reset_assert(reset, RESET_TIMEOUT_US_1MS);
if (ret != 0) {
panic();
}
udelay(2);
ret = stm32mp_reset_deassert(reset, RESET_TIMEOUT_US_1MS);
if (ret != 0) {
panic();
}
mdelay(1);
}
#endif
int stm32mp_uart_console_setup(void)
{
struct dt_node_info dt_uart_info;
unsigned int console_flags;
uint32_t clk_rate;
int result;
uint32_t boot_itf __unused;
uint32_t boot_instance __unused;
result = dt_get_stdout_uart_info(&dt_uart_info);
if ((result <= 0) ||
(dt_uart_info.status == DT_DISABLED) ||
(dt_uart_info.clock < 0) ||
(dt_uart_info.reset < 0)) {
return -ENODEV;
}
#if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2)
stm32_get_boot_interface(&boot_itf, &boot_instance);
if ((boot_itf == BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART) &&
(get_uart_address(boot_instance) == dt_uart_info.base)) {
return -EACCES;
}
#endif
#if defined(IMAGE_BL2)
if (dt_set_stdout_pinctrl() != 0) {
return -ENODEV;
}
#endif
stm32mp_clk_enable((unsigned long)dt_uart_info.clock);
#if defined(IMAGE_BL2)
reset_uart((uint32_t)dt_uart_info.reset);
#endif
clk_rate = stm32mp_clk_get_rate((unsigned long)dt_uart_info.clock);
if (console_stm32_register(dt_uart_info.base, clk_rate,
STM32MP_UART_BAUDRATE, &console) == 0) {
panic();
}
console_flags = CONSOLE_FLAG_BOOT | CONSOLE_FLAG_CRASH |
CONSOLE_FLAG_TRANSLATE_CRLF;
#if !defined(IMAGE_BL2) && defined(DEBUG)
console_flags |= CONSOLE_FLAG_RUNTIME;
#endif
console_set_scope(&console, console_flags);
return 0;
}
/*****************************************************************************
* plat_is_smccc_feature_available() - This function checks whether SMCCC
* feature is availabile for platform.

69
plat/st/stm32mp1/bl2_plat_setup.c
View file

@ -14,14 +14,12 @@
#include <common/bl_common.h>
#include <common/debug.h>
#include <common/desc_image_load.h>
#include <drivers/delay_timer.h>
#include <drivers/generic_delay_timer.h>
#include <drivers/mmc.h>
#include <drivers/st/bsec.h>
#include <drivers/st/stm32_console.h>
#include <drivers/st/stm32_iwdg.h>
#include <drivers/st/stm32_uart.h>
#include <drivers/st/stm32mp_pmic.h>
#include <drivers/st/stm32mp_reset.h>
#include <drivers/st/stm32mp1_clk.h>
#include <drivers/st/stm32mp1_pwr.h>
#include <drivers/st/stm32mp1_ram.h>
@ -32,12 +30,8 @@
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
#include <stm32mp1_context.h>
#include <stm32mp1_dbgmcu.h>
#define RESET_TIMEOUT_US_1MS 1000U
static console_t console;
static struct stm32mp_auth_ops stm32mp1_auth_ops;
static void print_reset_reason(void)
@ -167,11 +161,9 @@ void bl2_platform_setup(void)
void bl2_el3_plat_arch_setup(void)
{
int32_t result;
struct dt_node_info dt_uart_info;
const char *board_model;
boot_api_context_t *boot_context =
(boot_api_context_t *)stm32mp_get_boot_ctx_address();
uint32_t clk_rate;
uintptr_t pwr_base;
uintptr_t rcc_base;
@ -238,6 +230,16 @@ void bl2_el3_plat_arch_setup(void)
generic_delay_timer_init();
#if STM32MP_UART_PROGRAMMER
/* Disable programmer UART before changing clock tree */
if (boot_context->boot_interface_selected ==
BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART) {
uintptr_t uart_prog_addr =
get_uart_address(boot_context->boot_interface_instance);
stm32_uart_stop(uart_prog_addr);
}
#endif
if (stm32mp1_clk_probe() < 0) {
panic();
}
@ -248,45 +250,18 @@ void bl2_el3_plat_arch_setup(void)
stm32mp1_syscfg_init();
result = dt_get_stdout_uart_info(&dt_uart_info);
stm32_save_boot_interface(boot_context->boot_interface_selected,
boot_context->boot_interface_instance);
if ((result <= 0) ||
(dt_uart_info.status == 0U) ||
(dt_uart_info.clock < 0) ||
(dt_uart_info.reset < 0)) {
#if STM32MP_USB_PROGRAMMER
/* Deconfigure all UART RX pins configured by ROM code */
stm32mp1_deconfigure_uart_pins();
#endif
if (stm32mp_uart_console_setup() != 0) {
goto skip_console_init;
}
if (dt_set_stdout_pinctrl() != 0) {
goto skip_console_init;
}
stm32mp_clk_enable((unsigned long)dt_uart_info.clock);
if (stm32mp_reset_assert((uint32_t)dt_uart_info.reset,
RESET_TIMEOUT_US_1MS) != 0) {
panic();
}
udelay(2);
if (stm32mp_reset_deassert((uint32_t)dt_uart_info.reset,
RESET_TIMEOUT_US_1MS) != 0) {
panic();
}
mdelay(1);
clk_rate = stm32mp_clk_get_rate((unsigned long)dt_uart_info.clock);
if (console_stm32_register(dt_uart_info.base, clk_rate,
STM32MP_UART_BAUDRATE, &console) == 0) {
panic();
}
console_set_scope(&console, CONSOLE_FLAG_BOOT |
CONSOLE_FLAG_CRASH | CONSOLE_FLAG_TRANSLATE_CRLF);
stm32mp_print_cpuinfo();
board_model = dt_get_board_model();
@ -314,12 +289,6 @@ skip_console_init:
INFO("IWDG2 freeze error : %i\n", result);
}
if (stm32_save_boot_interface(boot_context->boot_interface_selected,
boot_context->boot_interface_instance) !=
0) {
ERROR("Cannot save boot interface\n");
}
stm32mp1_auth_ops.check_key = boot_context->bootrom_ecdsa_check_key;
stm32mp1_auth_ops.verify_signature =
boot_context->bootrom_ecdsa_verify_signature;

14
plat/st/stm32mp1/include/stm32mp1_context.h
View file

@ -1,14 +0,0 @@
/*
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef STM32MP1_CONTEXT_H
#define STM32MP1_CONTEXT_H
#include <stdint.h>
int stm32_save_boot_interface(uint32_t interface, uint32_t instance);
#endif /* STM32MP1_CONTEXT_H */

2
plat/st/stm32mp1/include/stm32mp1_private.h
View file

@ -21,6 +21,8 @@ void stm32mp1_syscfg_init(void);
void stm32mp1_syscfg_enable_io_compensation(void);
void stm32mp1_syscfg_disable_io_compensation(void);
void stm32mp1_deconfigure_uart_pins(void);
#if STM32MP_USE_STM32IMAGE
uint32_t stm32mp_get_ddr_ns_size(void);
#endif /* STM32MP_USE_STM32IMAGE */

27
plat/st/stm32mp1/platform.mk
View file

@ -28,6 +28,8 @@ ifeq ($(AARCH32_SP),sp_min)
TF_CFLAGS += -mfloat-abi=soft
endif
TF_CFLAGS += -Wsign-compare
# Not needed for Cortex-A7
WORKAROUND_CVE_2017_5715:= 0
@ -124,13 +126,13 @@ endif
# Enable flags for C files
$(eval $(call assert_booleans,\
$(sort \
PLAT_XLAT_TABLES_DYNAMIC \
STM32MP_EMMC \
STM32MP_SDMMC \
STM32MP_EMMC_BOOT \
STM32MP_RAW_NAND \
STM32MP_SDMMC \
STM32MP_SPI_NAND \
STM32MP_SPI_NOR \
STM32MP_EMMC_BOOT \
PLAT_XLAT_TABLES_DYNAMIC \
STM32MP_UART_PROGRAMMER \
STM32MP_USB_PROGRAMMER \
STM32MP_USE_STM32IMAGE \
@ -138,23 +140,23 @@ $(eval $(call assert_booleans,\
$(eval $(call assert_numerics,\
$(sort \
STM32_TF_A_COPIES \
PLAT_PARTITION_MAX_ENTRIES \
STM32_TF_A_COPIES \
STM32_TF_VERSION \
)))
$(eval $(call add_defines,\
$(sort \
STM32_TF_VERSION \
STM32MP_EMMC \
STM32MP_SDMMC \
STM32MP_RAW_NAND \
STM32MP_SPI_NAND \
STM32MP_SPI_NOR \
STM32MP_EMMC_BOOT \
PLAT_PARTITION_MAX_ENTRIES \
PLAT_XLAT_TABLES_DYNAMIC \
STM32_TF_A_COPIES \
PLAT_PARTITION_MAX_ENTRIES \
STM32_TF_VERSION \
STM32MP_EMMC \
STM32MP_EMMC_BOOT \
STM32MP_RAW_NAND \
STM32MP_SDMMC \
STM32MP_SPI_NAND \
STM32MP_SPI_NOR \
STM32MP_UART_PROGRAMMER \
STM32MP_USB_PROGRAMMER \
STM32MP_USE_STM32IMAGE \
@ -200,7 +202,6 @@ PLAT_BL_COMMON_SOURCES += drivers/arm/tzc/tzc400.c \
drivers/st/pmic/stpmic1.c \
drivers/st/reset/stm32mp1_reset.c \
plat/st/common/stm32mp_dt.c \
plat/st/stm32mp1/stm32mp1_context.c \
plat/st/stm32mp1/stm32mp1_dbgmcu.c \
plat/st/stm32mp1/stm32mp1_helper.S \
plat/st/stm32mp1/stm32mp1_syscfg.c

24
plat/st/stm32mp1/sp_min/sp_min_setup.c
View file

@ -18,7 +18,6 @@
#include <drivers/generic_delay_timer.h>
#include <drivers/st/bsec.h>
#include <drivers/st/etzpc.h>
#include <drivers/st/stm32_console.h>
#include <drivers/st/stm32_gpio.h>
#include <drivers/st/stm32_iwdg.h>
#include <drivers/st/stm32mp1_clk.h>
@ -36,8 +35,6 @@
******************************************************************************/
static entry_point_info_t bl33_image_ep_info;
static console_t console;
/*******************************************************************************
* Interrupt handler for FIQ (secure IRQ)
******************************************************************************/
@ -115,8 +112,6 @@ static void stm32mp1_etzpc_early_setup(void)
void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
struct dt_node_info dt_uart_info;
int result;
bl_params_t *params_from_bl2 = (bl_params_t *)arg0;
#if STM32MP_USE_STM32IMAGE
uintptr_t dt_addr = STM32MP_DTB_BASE;
@ -174,24 +169,7 @@ void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
panic();
}
result = dt_get_stdout_uart_info(&dt_uart_info);
if ((result > 0) && (dt_uart_info.status != 0U)) {
unsigned int console_flags;
if (console_stm32_register(dt_uart_info.base, 0,
STM32MP_UART_BAUDRATE, &console) ==
0) {
panic();
}
console_flags = CONSOLE_FLAG_BOOT | CONSOLE_FLAG_CRASH |
CONSOLE_FLAG_TRANSLATE_CRLF;
#ifdef DEBUG
console_flags |= CONSOLE_FLAG_RUNTIME;
#endif
console_set_scope(&console, console_flags);
}
(void)stm32mp_uart_console_setup();
stm32mp1_etzpc_early_setup();
}

35
plat/st/stm32mp1/stm32mp1_context.c
View file

@ -1,35 +0,0 @@
/*
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <errno.h>
#include <platform_def.h>
#include <drivers/st/stm32mp1_clk.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <lib/mmio.h>
#include <stm32mp1_context.h>
#define TAMP_BOOT_ITF_BACKUP_REG_ID U(20)
#define TAMP_BOOT_ITF_MASK U(0x0000FF00)
#define TAMP_BOOT_ITF_SHIFT 8
int stm32_save_boot_interface(uint32_t interface, uint32_t instance)
{
uint32_t bkpr_itf_idx = tamp_bkpr(TAMP_BOOT_ITF_BACKUP_REG_ID);
stm32mp_clk_enable(RTCAPB);
mmio_clrsetbits_32(bkpr_itf_idx,
TAMP_BOOT_ITF_MASK,
((interface << 4) | (instance & 0xFU)) <<
TAMP_BOOT_ITF_SHIFT);
stm32mp_clk_disable(RTCAPB);
return 0;
}

102
plat/st/stm32mp1/stm32mp1_private.c
View file

@ -6,13 +6,14 @@
#include <assert.h>
#include <drivers/st/stm32_gpio.h>
#include <drivers/st/stm32_iwdg.h>
#include <libfdt.h>
#include <lib/mmio.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <platform_def.h>
#include <drivers/st/stm32_iwdg.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
/* Internal layout of the 32bit OTP word board_id */
#define BOARD_ID_BOARD_NB_MASK GENMASK(31, 16)
#define BOARD_ID_BOARD_NB_SHIFT 16
@ -34,6 +35,10 @@
BOARD_ID_VARFG_SHIFT)
#define BOARD_ID2BOM(_id) ((_id) & BOARD_ID_BOM_MASK)
#define TAMP_BOOT_MODE_BACKUP_REG_ID U(20)
#define TAMP_BOOT_MODE_ITF_MASK U(0x0000FF00)
#define TAMP_BOOT_MODE_ITF_SHIFT 8
#if defined(IMAGE_BL2)
#define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \
STM32MP_SYSRAM_SIZE, \
@ -120,6 +125,15 @@ uint32_t stm32_get_gpio_bank_offset(unsigned int bank)
return bank * GPIO_BANK_OFFSET;
}
bool stm32_gpio_is_secure_at_reset(unsigned int bank)
{
if (bank == GPIO_BANK_Z) {
return true;
}
return false;
}
unsigned long stm32_get_gpio_bank_clock(unsigned int bank)
{
if (bank == GPIO_BANK_Z) {
@ -153,7 +167,7 @@ int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank)
}
}
#if STM32MP_UART_PROGRAMMER
#if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2)
/*
* UART Management
*/
@ -179,6 +193,53 @@ uintptr_t get_uart_address(uint32_t instance_nb)
}
#endif
#if STM32MP_USB_PROGRAMMER
struct gpio_bank_pin_list {
uint32_t bank;
uint32_t pin;
};
static const struct gpio_bank_pin_list gpio_list[] = {
{ /* USART2_RX: GPIOA3 */
.bank = 0U,
.pin = 3U,
},
{ /* USART3_RX: GPIOB12 */
.bank = 1U,
.pin = 12U,
},
{ /* UART4_RX: GPIOB2 */
.bank = 1U,
.pin = 2U,
},
{ /* UART5_RX: GPIOB4 */
.bank = 1U,
.pin = 5U,
},
{ /* USART6_RX: GPIOC7 */
.bank = 2U,
.pin = 7U,
},
{ /* UART7_RX: GPIOF6 */
.bank = 5U,
.pin = 6U,
},
{ /* UART8_RX: GPIOE0 */
.bank = 4U,
.pin = 0U,
},
};
void stm32mp1_deconfigure_uart_pins(void)
{
size_t i;
for (i = 0U; i < ARRAY_SIZE(gpio_list); i++) {
set_gpio_reset_cfg(gpio_list[i].bank, gpio_list[i].pin);
}
}
#endif
uint32_t stm32mp_get_chip_version(void)
{
uint32_t version = 0U;
@ -500,3 +561,36 @@ uint32_t stm32mp_get_ddr_ns_size(void)
return ddr_ns_size;
}
#endif /* STM32MP_USE_STM32IMAGE */
void stm32_save_boot_interface(uint32_t interface, uint32_t instance)
{
uint32_t bkpr_itf_idx = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID);
stm32mp_clk_enable(RTCAPB);
mmio_clrsetbits_32(bkpr_itf_idx,
TAMP_BOOT_MODE_ITF_MASK,
((interface << 4) | (instance & 0xFU)) <<
TAMP_BOOT_MODE_ITF_SHIFT);
stm32mp_clk_disable(RTCAPB);
}
void stm32_get_boot_interface(uint32_t *interface, uint32_t *instance)
{
static uint32_t itf;
if (itf == 0U) {
uint32_t bkpr = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID);
stm32mp_clk_enable(RTCAPB);
itf = (mmio_read_32(bkpr) & TAMP_BOOT_MODE_ITF_MASK) >>
TAMP_BOOT_MODE_ITF_SHIFT;
stm32mp_clk_disable(RTCAPB);
}
*interface = itf >> 4;
*instance = itf & 0xFU;
}