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feat(ti-k3): add support for J784S4 SoCs

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The J784S4 SoC has two quad Cortex-A72 core clusters. This is the first
SoC in the K3 family with Quad cores in a A-72 cluster. So, a new board
configuration is introduced to support quad core clusters on the J784S4
SoC of the K3 family of devices.

See J784S4 Technical Reference Manual (SPRUJ52 - JUNE 2022)
for further details: http://www.ti.com/lit/zip/spruj52

Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Change-Id: I0ed1f14ab32a56ae06e3df3161ace4597d14a48d
This commit is contained in:
Hari Nagalla 2022-08-22 14:04:52 -05:00
parent 00460e7dfa
commit 4a566b26ae
2 changed files with 67 additions and 0 deletions
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24
plat/ti/k3/board/j784s4/board.mk Normal file
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#
# Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
BL32_BASE ?= 0x9e800000
$(eval $(call add_define,BL32_BASE))
PRELOADED_BL33_BASE ?= 0x80080000
$(eval $(call add_define,PRELOADED_BL33_BASE))
K3_HW_CONFIG_BASE ?= 0x82000000
$(eval $(call add_define,K3_HW_CONFIG_BASE))
# Define sec_proxy usage as the full prioritized communication scheme
K3_SEC_PROXY_LITE := 0
$(eval $(call add_define,K3_SEC_PROXY_LITE))
# System coherency is managed in hardware
USE_COHERENT_MEM := 1
PLAT_INCLUDES += \
-Iplat/ti/k3/board/j784s4/include \

43
plat/ti/k3/board/j784s4/include/board_def.h Normal file
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/*
* Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef BOARD_DEF_H
#define BOARD_DEF_H
#include <lib/utils_def.h>
/* The ports must be in order and contiguous */
#define K3_CLUSTER0_CORE_COUNT U(4)
#define K3_CLUSTER1_CORE_COUNT U(4)
#define K3_CLUSTER2_CORE_COUNT U(0)
#define K3_CLUSTER3_CORE_COUNT U(0)
/*
* This RAM will be used for the bootloader including code, bss, and stacks.
* It may need to be increased if BL31 grows in size.
*
* The link addresses are determined by SEC_SRAM_BASE + offset.
* When ENABLE_PIE is set, the TF images can be loaded anywhere, so
* SEC_SRAM_BASE is really arbitrary.
*
* When ENABLE_PIE is unset, SEC_SRAM_BASE should be chosen so that
* it matches to the physical address where BL31 is loaded, that is,
* SEC_SRAM_BASE should be the base address of the RAM region.
*
* Lets make things explicit by mapping SRAM_BASE to 0x0 since ENABLE_PIE is
* defined as default for our platform.
*/
#define SEC_SRAM_BASE UL(0x00000000) /* PIE remapped on fly */
#define SEC_SRAM_SIZE UL(0x00020000) /* 128k */
#define PLAT_MAX_OFF_STATE U(2)
#define PLAT_MAX_RET_STATE U(1)
#define PLAT_PROC_START_ID U(32)
#define PLAT_PROC_DEVICE_START_ID U(202)
#define PLAT_CLUSTER_DEVICE_START_ID U(198)
#endif /* BOARD_DEF_H */