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drivers: Add SPI Nor flash support
Add SPI Nor flash support Change-Id: I0cde3fdb4dcad5bcaf445b3bb48e279332bd28af Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
This commit is contained in:
Sheetal Tigadoli
parent
e3ee7b7dc8
commit
49dec7f7f2
5 changed files with 482 additions and 0 deletions
308
drivers/brcm/spi_flash.c
Normal file
308
drivers/brcm/spi_flash.c
Normal file
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@ -0,0 +1,308 @@
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/*
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* Copyright (c) 2019-2020, Broadcom
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdbool.h>
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#include <stddef.h>
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#include <stdint.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <errno.h>
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#include <sf.h>
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#include <spi.h>
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#define SPI_FLASH_CMD_LEN 4
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#define QSPI_WAIT_TIMEOUT_US 200000U /* usec */
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#define FINFO(jedec_id, ext_id, _sector_size, _n_sectors, _page_size, _flags) \
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.id = { \
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((jedec_id) >> 16) & 0xff, \
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((jedec_id) >> 8) & 0xff, \
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(jedec_id) & 0xff, \
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((ext_id) >> 8) & 0xff, \
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(ext_id) & 0xff, \
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}, \
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.id_len = (!(jedec_id) ? 0 : (3 + ((ext_id) ? 2 : 0))), \
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.sector_size = (_sector_size), \
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.n_sectors = (_n_sectors), \
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.page_size = _page_size, \
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.flags = (_flags),
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/* SPI/QSPI flash device params structure */
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const struct spi_flash_info spi_flash_ids[] = {
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{"W25Q64CV", FINFO(0xef4017, 0x0, 64 * 1024, 128, 256, WR_QPP | SECT_4K)},
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{"W25Q64DW", FINFO(0xef6017, 0x0, 64 * 1024, 128, 256, WR_QPP | SECT_4K)},
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{"W25Q32", FINFO(0xef4016, 0x0, 64 * 1024, 64, 256, SECT_4K)},
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{"MX25l3205D", FINFO(0xc22016, 0x0, 64 * 1024, 64, 256, SECT_4K)},
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};
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static void spi_flash_addr(uint32_t addr, uint8_t *cmd)
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{
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/*
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* cmd[0] holds a SPI Flash command, stored earlier
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* cmd[1/2/3] holds 24bit flash address
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*/
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cmd[1] = addr >> 16;
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cmd[2] = addr >> 8;
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cmd[3] = addr >> 0;
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}
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static const struct spi_flash_info *spi_flash_read_id(void)
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{
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const struct spi_flash_info *info;
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uint8_t id[SPI_FLASH_MAX_ID_LEN];
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int ret;
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ret = spi_flash_cmd(CMD_READ_ID, id, SPI_FLASH_MAX_ID_LEN);
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if (ret < 0) {
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ERROR("SF: Error %d reading JEDEC ID\n", ret);
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return NULL;
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}
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for (info = spi_flash_ids; info->name != NULL; info++) {
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if (info->id_len) {
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if (!memcmp(info->id, id, info->id_len))
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return info;
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}
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}
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printf("SF: unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
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id[0], id[1], id[2]);
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return NULL;
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}
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/* Enable writing on the SPI flash */
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static inline int spi_flash_cmd_write_enable(struct spi_flash *flash)
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{
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return spi_flash_cmd(CMD_WRITE_ENABLE, NULL, 0);
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}
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static int spi_flash_cmd_wait(struct spi_flash *flash)
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{
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uint8_t cmd;
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uint32_t i;
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uint8_t status;
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int ret;
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i = 0;
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while (1) {
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cmd = CMD_RDSR;
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ret = spi_flash_cmd_read(&cmd, 1, &status, 1);
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if (ret < 0) {
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ERROR("SF: cmd wait failed\n");
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break;
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}
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if (!(status & STATUS_WIP))
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break;
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i++;
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if (i >= QSPI_WAIT_TIMEOUT_US) {
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ERROR("SF: cmd wait timeout\n");
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ret = -1;
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break;
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}
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udelay(1);
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}
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return ret;
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}
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static int spi_flash_write_common(struct spi_flash *flash, const uint8_t *cmd,
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size_t cmd_len, const void *buf,
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size_t buf_len)
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{
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int ret;
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ret = spi_flash_cmd_write_enable(flash);
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if (ret < 0) {
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ERROR("SF: enabling write failed\n");
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return ret;
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}
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ret = spi_flash_cmd_write(cmd, cmd_len, buf, buf_len);
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if (ret < 0) {
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ERROR("SF: write cmd failed\n");
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return ret;
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}
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ret = spi_flash_cmd_wait(flash);
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if (ret < 0) {
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ERROR("SF: write timed out\n");
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return ret;
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}
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return ret;
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}
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static int spi_flash_read_common(const uint8_t *cmd, size_t cmd_len,
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void *data, size_t data_len)
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{
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int ret;
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ret = spi_flash_cmd_read(cmd, cmd_len, data, data_len);
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if (ret < 0) {
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ERROR("SF: read cmd failed\n");
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return ret;
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}
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return ret;
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}
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int spi_flash_read(struct spi_flash *flash, uint32_t offset,
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uint32_t len, void *data)
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{
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uint32_t read_len = 0, read_addr;
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uint8_t cmd[SPI_FLASH_CMD_LEN];
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int ret;
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ret = spi_claim_bus();
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if (ret) {
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ERROR("SF: unable to claim SPI bus\n");
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return ret;
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}
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cmd[0] = CMD_READ_NORMAL;
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while (len) {
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read_addr = offset;
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read_len = MIN(flash->page_size, (len - read_len));
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spi_flash_addr(read_addr, cmd);
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ret = spi_flash_read_common(cmd, sizeof(cmd), data, read_len);
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if (ret < 0) {
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ERROR("SF: read failed\n");
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break;
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}
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offset += read_len;
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len -= read_len;
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data += read_len;
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}
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SPI_DEBUG("SF read done\n");
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spi_release_bus();
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return ret;
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}
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int spi_flash_write(struct spi_flash *flash, uint32_t offset,
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uint32_t len, void *buf)
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{
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unsigned long byte_addr, page_size;
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uint8_t cmd[SPI_FLASH_CMD_LEN];
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uint32_t chunk_len, actual;
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uint32_t write_addr;
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int ret;
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ret = spi_claim_bus();
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if (ret) {
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ERROR("SF: unable to claim SPI bus\n");
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return ret;
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}
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page_size = flash->page_size;
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cmd[0] = flash->write_cmd;
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for (actual = 0; actual < len; actual += chunk_len) {
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write_addr = offset;
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byte_addr = offset % page_size;
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chunk_len = MIN(len - actual,
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(uint32_t)(page_size - byte_addr));
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spi_flash_addr(write_addr, cmd);
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SPI_DEBUG("SF:0x%p=>cmd:{0x%02x 0x%02x%02x%02x} chunk_len:%d\n",
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buf + actual, cmd[0], cmd[1],
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cmd[2], cmd[3], chunk_len);
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ret = spi_flash_write_common(flash, cmd, sizeof(cmd),
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buf + actual, chunk_len);
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if (ret < 0) {
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ERROR("SF: write cmd failed\n");
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break;
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}
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offset += chunk_len;
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}
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SPI_DEBUG("SF write done\n");
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spi_release_bus();
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return ret;
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}
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int spi_flash_erase(struct spi_flash *flash, uint32_t offset, uint32_t len)
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{
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uint8_t cmd[SPI_FLASH_CMD_LEN];
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uint32_t erase_size, erase_addr;
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int ret;
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erase_size = flash->erase_size;
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if (offset % erase_size || len % erase_size) {
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ERROR("SF: Erase offset/length not multiple of erase size\n");
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return -1;
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}
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ret = spi_claim_bus();
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if (ret) {
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ERROR("SF: unable to claim SPI bus\n");
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return ret;
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}
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cmd[0] = flash->erase_cmd;
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while (len) {
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erase_addr = offset;
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spi_flash_addr(erase_addr, cmd);
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SPI_DEBUG("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
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cmd[2], cmd[3], erase_addr);
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ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
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if (ret < 0) {
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ERROR("SF: erase failed\n");
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break;
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}
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offset += erase_size;
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len -= erase_size;
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}
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SPI_DEBUG("sf erase done\n");
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spi_release_bus();
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return ret;
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}
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int spi_flash_probe(struct spi_flash *flash)
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{
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const struct spi_flash_info *info = NULL;
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int ret;
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ret = spi_claim_bus();
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if (ret) {
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ERROR("SF: Unable to claim SPI bus\n");
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ERROR("SF: probe failed\n");
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return ret;
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}
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info = spi_flash_read_id();
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if (!info)
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goto probe_fail;
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INFO("Flash Name: %s sectors %x, sec size %x\n",
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info->name, info->n_sectors,
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info->sector_size);
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flash->size = info->n_sectors * info->sector_size;
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flash->sector_size = info->sector_size;
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flash->page_size = info->page_size;
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flash->flags = info->flags;
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flash->read_cmd = CMD_READ_NORMAL;
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flash->write_cmd = CMD_PAGE_PROGRAM;
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flash->erase_cmd = CMD_ERASE_64K;
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flash->erase_size = ERASE_SIZE_64K;
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probe_fail:
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spi_release_bus();
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return ret;
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}
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60
drivers/brcm/spi_sf.c
Normal file
60
drivers/brcm/spi_sf.c
Normal file
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/*
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* Copyright (c) 2019-2020, Broadcom
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include <spi.h>
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#define BITS_PER_BYTE 8
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#define CMD_LEN1 1
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static int spi_flash_read_write(const uint8_t *cmd,
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size_t cmd_len,
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const uint8_t *data_out,
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uint8_t *data_in,
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size_t data_len)
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{
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unsigned long flags = SPI_XFER_BEGIN;
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int ret;
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if (data_len == 0)
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flags |= SPI_XFER_END;
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ret = spi_xfer(cmd_len * BITS_PER_BYTE, cmd, NULL, flags);
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if (ret) {
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ERROR("SF: Failed to send command (%zu bytes): %d\n",
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cmd_len, ret);
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} else if (data_len != 0) {
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ret = spi_xfer(data_len * BITS_PER_BYTE, data_out,
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data_in, SPI_XFER_END);
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if (ret)
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ERROR("SF: Failed to transfer %zu bytes of data: %d\n",
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data_len, ret);
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}
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return ret;
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}
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int spi_flash_cmd_read(const uint8_t *cmd,
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size_t cmd_len,
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void *data,
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size_t data_len)
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{
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return spi_flash_read_write(cmd, cmd_len, NULL, data, data_len);
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}
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int spi_flash_cmd(uint8_t cmd, void *response, size_t len)
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{
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return spi_flash_cmd_read(&cmd, CMD_LEN1, response, len);
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}
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int spi_flash_cmd_write(const uint8_t *cmd,
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size_t cmd_len,
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const void *data,
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size_t data_len)
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{
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return spi_flash_read_write(cmd, cmd_len, data, NULL, data_len);
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}
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90
include/drivers/brcm/sf.h
Normal file
90
include/drivers/brcm/sf.h
Normal file
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/*
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* Copyright (c) 2019-2020, Broadcom
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SF_H
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#define SF_H
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#include <stdint.h>
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#include <stddef.h>
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#ifdef SPI_DEBUG
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#define SPI_DEBUG(fmt, ...) INFO(fmt, ##__VA_ARGS__)
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#else
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#define SPI_DEBUG(fmt, ...)
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#endif
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#define SPI_FLASH_MAX_ID_LEN 6
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#define CMD_WRSR 0x01 /* Write status register */
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#define CMD_PAGE_PROGRAM 0x02
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#define CMD_READ_NORMAL 0x03
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#define CMD_RDSR 0x05
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#define CMD_WRITE_ENABLE 0x06
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#define CMD_RDFSR 0x70
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#define CMD_READ_ID 0x9f
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#define CMD_ERASE_4K 0x20
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#define CMD_ERASE_64K 0xd8
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#define ERASE_SIZE_64K (64 * 1024)
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/* Common status */
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#define STATUS_WIP BIT(0)
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struct spi_flash {
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struct spi_slave *spi;
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uint32_t size;
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uint32_t page_size;
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uint32_t sector_size;
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uint32_t erase_size;
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uint8_t erase_cmd;
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uint8_t read_cmd;
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uint8_t write_cmd;
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uint8_t flags;
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};
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struct spi_flash_info {
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const char *name;
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/*
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* This array stores the ID bytes.
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* The first three bytes are the JEDIC ID.
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* JEDEC ID zero means "no ID" (mostly older chips).
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*/
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uint8_t id[SPI_FLASH_MAX_ID_LEN];
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uint8_t id_len;
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uint32_t sector_size;
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uint32_t n_sectors;
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uint16_t page_size;
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uint8_t flags;
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};
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/* Enum list - Full read commands */
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enum spi_read_cmds {
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ARRAY_SLOW = BIT(0),
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ARRAY_FAST = BIT(1),
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DUAL_OUTPUT_FAST = BIT(2),
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DUAL_IO_FAST = BIT(3),
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QUAD_OUTPUT_FAST = BIT(4),
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QUAD_IO_FAST = BIT(5),
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};
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/* sf param flags */
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enum spi_param_flag {
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SECT_4K = BIT(0),
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SECT_32K = BIT(1),
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E_FSR = BIT(2),
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SST_BP = BIT(3),
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SST_WP = BIT(4),
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WR_QPP = BIT(5),
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};
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int spi_flash_cmd_read(const uint8_t *cmd, size_t cmd_len,
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void *data, size_t data_len);
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int spi_flash_cmd(uint8_t cmd, void *response, size_t len);
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int spi_flash_cmd_write(const uint8_t *cmd, size_t cmd_len,
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const void *data, size_t data_len);
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#endif
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18
include/drivers/brcm/spi_flash.h
Normal file
18
include/drivers/brcm/spi_flash.h
Normal file
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@ -0,0 +1,18 @@
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/*
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* Copyright (c) 2019-2020, Broadcom
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SPI_FLASH_H
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#define SPI_FLASH_H
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#include <sf.h>
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int spi_flash_probe(struct spi_flash *flash);
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int spi_flash_erase(struct spi_flash *flash, uint32_t offset, uint32_t len);
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int spi_flash_write(struct spi_flash *flash, uint32_t offset,
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uint32_t len, void *buf);
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int spi_flash_read(struct spi_flash *flash, uint32_t offset,
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uint32_t len, void *data);
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#endif /* _SPI_FLASH_H_ */
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|
|
@ -169,6 +169,12 @@ PLAT_BL_COMMON_SOURCES += drivers/brcm/spi/iproc_spi.c \
|
|||
drivers/brcm/spi/iproc_qspi.c
|
||||
endif
|
||||
|
||||
# Add spi nor/flash driver
|
||||
ifeq (${DRIVER_SPI_NOR_ENABLE},1)
|
||||
PLAT_BL_COMMON_SOURCES += drivers/brcm/spi_sf.c \
|
||||
drivers/brcm/spi_flash.c
|
||||
endif
|
||||
|
||||
ifeq (${DRIVER_OCOTP_ENABLE},1)
|
||||
$(eval $(call add_define,DRIVER_OCOTP_ENABLE))
|
||||
BL2_SOURCES += drivers/brcm/ocotp.c
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue