Djam/arm-trusted-firmware
1
0
Fork 0
mirror of https://github.com/ARM-software/arm-trusted-firmware.git synced 2025-04-23 13:36:05 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

Merge changes from topic "sami/550_fix_n1sdp_issues_v1" into integration

Browse source 
* changes:
  N1SDP: Initialise CNTFRQ in Non Secure CNTBaseN
  N1SDP: Fix DRAM2 start address
  Add option for defining platform DRAM2 base
  Disable speculative loads only if SSBS is supported
This commit is contained in:
Soby Mathew 2019-05-16 08:33:56 +00:00 • committed by TrustedFirmware Code Review
commit 482fc9c888
7 changed files with 36 additions and 13 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
include/plat/arm/board/common/board_css_def.h
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -54,7 +54,7 @@
* Required platform porting definitions common to all ARM CSS-based * Required platform porting definitions common to all ARM CSS-based
* development platforms * development platforms
*/ */
#define PLAT_ARM_DRAM2_BASE ULL(0x880000000)
#define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) #define PLAT_ARM_DRAM2_SIZE ULL(0x180000000)
/* UART related constants */ /* UART related constants */

4
include/plat/arm/common/arm_def.h
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -148,7 +148,7 @@
#define ARM_DRAM1_END (ARM_DRAM1_BASE + \ #define ARM_DRAM1_END (ARM_DRAM1_BASE + \
ARM_DRAM1_SIZE - 1) ARM_DRAM1_SIZE - 1)
#define ARM_DRAM2_BASE UL(0x880000000) #define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE
#define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE
#define ARM_DRAM2_END (ARM_DRAM2_BASE + \ #define ARM_DRAM2_END (ARM_DRAM2_BASE + \
ARM_DRAM2_SIZE - 1) ARM_DRAM2_SIZE - 1)

24
lib/cpus/aarch64/neoverse_n1.S
View file

@ -49,11 +49,31 @@ func check_errata_1043202
b cpu_rev_var_ls b cpu_rev_var_ls
endfunc check_errata_1043202 endfunc check_errata_1043202
/* --------------------------------------------------
* Disable speculative loads if Neoverse N1 supports
* SSBS.
*
* Shall clobber: x0.
* --------------------------------------------------
*/
func neoverse_n1_disable_speculative_loads
/* Check if the PE implements SSBS */
mrs x0, id_aa64pfr1_el1
tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT)
b.eq 1f
/* Disable speculative loads */
msr SSBS, xzr
isb
1:
ret
endfunc neoverse_n1_disable_speculative_loads
func neoverse_n1_reset_func func neoverse_n1_reset_func
mov x19, x30 mov x19, x30
/* Disables speculative loads */ bl neoverse_n1_disable_speculative_loads
msr SSBS, xzr
/* Forces all cacheable atomic instructions to be near */ /* Forces all cacheable atomic instructions to be near */
mrs x0, NEOVERSE_N1_CPUACTLR2_EL1 mrs x0, NEOVERSE_N1_CPUACTLR2_EL1

1
plat/arm/board/fvp/include/platform_def.h
View file

@ -48,6 +48,7 @@
/* No SCP in FVP */ /* No SCP in FVP */
#define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0) #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0)
#define PLAT_ARM_DRAM2_BASE ULL(0x880000000)
#define PLAT_ARM_DRAM2_SIZE UL(0x80000000) #define PLAT_ARM_DRAM2_SIZE UL(0x80000000)
/* /*

3
plat/arm/board/fvp_ve/include/platform_def.h
View file

@ -25,7 +25,7 @@
#define ARM_DRAM1_END (ARM_DRAM1_BASE + \ #define ARM_DRAM1_END (ARM_DRAM1_BASE + \
ARM_DRAM1_SIZE - 1) ARM_DRAM1_SIZE - 1)
#define ARM_DRAM2_BASE UL(0x880000000) #define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE
#define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE
#define ARM_DRAM2_END (ARM_DRAM2_BASE + \ #define ARM_DRAM2_END (ARM_DRAM2_BASE + \
ARM_DRAM2_SIZE - 1) ARM_DRAM2_SIZE - 1)
@ -230,6 +230,7 @@
#define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000 #define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000
#define PLAT_ARM_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */ #define PLAT_ARM_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */
#define PLAT_ARM_DRAM2_BASE ULL(0x880000000)
#define PLAT_ARM_DRAM2_SIZE ULL(0x80000000) #define PLAT_ARM_DRAM2_SIZE ULL(0x80000000)
/* /*

3
plat/arm/board/n1sdp/include/platform_def.h
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -24,6 +24,7 @@
#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE
#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ
#define PLAT_ARM_DRAM2_BASE ULL(0x8080000000)
#define PLAT_ARM_DRAM2_SIZE ULL(0x780000000) #define PLAT_ARM_DRAM2_SIZE ULL(0x780000000)
#if CSS_USE_SCMI_SDS_DRIVER #if CSS_USE_SCMI_SDS_DRIVER

10
plat/arm/common/arm_common.c
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -127,12 +127,12 @@ void arm_configure_sys_timer(void)
*/ */
mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTCTLBASE_CNTFRQ, freq_val); mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTCTLBASE_CNTFRQ, freq_val);
#ifdef PLAT_juno #if defined(PLAT_juno) || defined(PLAT_n1sdp)
/* /*
* Initialize CNTFRQ register in Non-secure CNTBase frame. * Initialize CNTFRQ register in Non-secure CNTBase frame.
* This is only required for Juno, because it doesn't follow ARM ARM * This is only required for Juno and N1SDP, because they do not
* in that the value updated in CNTFRQ is not reflected in * follow ARM ARM in that the value updated in CNTFRQ is not
* CNTBASEN_CNTFRQ. Hence update the value manually. * reflected in CNTBASEN_CNTFRQ. Hence update the value manually.
*/ */
mmio_write_32(ARM_SYS_CNT_BASE_NS + CNTBASEN_CNTFRQ, freq_val); mmio_write_32(ARM_SYS_CNT_BASE_NS + CNTBASEN_CNTFRQ, freq_val);
#endif #endif