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GIC: Ensure SGIs and PPIs are Group0 before setup
The legacy GIC driver assumes that the SGIs and PPIs are Group0 during initialization. This is true if the driver is the first one to initialize the GIC hardware after reset. But in some cases, earlier BL stages could have already initialized the GIC hardware which means that SGI and PPI configuration are not the expected reset values causing assertion failure in `gicd_set_ipriorityr()`. This patch explicitly resets the SGI and PPI to Group0 prior to their initialization in the driver. The same patch is not done in the GICv2-only driver because unlike in the legacy driver, `gicd_set_ipriorityr()` of GICv2 driver doesn't enforce this policy and the appropriate group is set irrespective of the initial value. Fixes ARM-software/tf-issues#396 Change-Id: I521d35caa37470ce542c796c2ba99716e4763105
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1 changed files with 6 additions and 2 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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@ -205,10 +205,14 @@ void arm_gic_pcpu_distif_setup(void)
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assert(g_irq_sec_ptr);
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sec_ppi_sgi_mask = 0;
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/* Ensure all SGIs and PPIs are Group0 to begin with */
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gicd_write_igroupr(g_gicd_base, 0, 0);
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for (index = 0; index < g_num_irqs; index++) {
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irq_num = g_irq_sec_ptr[index];
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if (irq_num < MIN_SPI_ID) {
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/* We have an SGI or a PPI. They are Group0 at reset */
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/* We have an SGI or a PPI */
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sec_ppi_sgi_mask |= 1U << irq_num;
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gicd_set_ipriorityr(g_gicd_base, irq_num,
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GIC_HIGHEST_SEC_PRIORITY);
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