Djam/arm-trusted-firmware
1
0
Fork 0
mirror of https://github.com/ARM-software/arm-trusted-firmware.git synced 2025-04-27 07:15:20 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

fix(sme): add missing ISBs

Browse source 
EL3 is configured to trap accesses to SME registers (via
CPTR_EL3.ESM=0). To allow SME instructions, this needs to be temporarily
disabled before changing system registers. If the PE delays the effects
of writes to system registers then accessing the SME registers will trap
without an isb. This patch adds the isb to restore functionality.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I8ee5ecaec978dde2525631daa682a182ad8f7f04
This commit is contained in:
Boyan Karatotev 2022-10-13 13:51:05 +01:00
parent c45d2febb9
commit 46e92f2862
1 changed files with 2 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
lib/extensions/sme/sme.c
View file

@ -58,6 +58,7 @@ void sme_enable(cpu_context_t *context)
/* Set CPTR_EL3.ESM bit so we can write SMCR_EL3 without trapping. */ /* Set CPTR_EL3.ESM bit so we can write SMCR_EL3 without trapping. */
cptr_el3 = read_cptr_el3(); cptr_el3 = read_cptr_el3();
write_cptr_el3(cptr_el3 | ESM_BIT); write_cptr_el3(cptr_el3 | ESM_BIT);
isb();
/* /*
* Set the max LEN value and FA64 bit. This register is set up globally * Set the max LEN value and FA64 bit. This register is set up globally
@ -73,6 +74,7 @@ void sme_enable(cpu_context_t *context)
/* Reset CPTR_EL3 value. */ /* Reset CPTR_EL3 value. */
write_cptr_el3(cptr_el3); write_cptr_el3(cptr_el3);
isb();
/* Enable SVE/FPU in addition to SME. */ /* Enable SVE/FPU in addition to SME. */
sve_enable(context); sve_enable(context);