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Add initial CPU support for Cortex-Helios

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Change-Id: Ic0486131c493632eadf329f80b0b5904aed5e4ef
Signed-off-by: Joel Hutton <joel.hutton@arm.com>
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
This commit is contained in:
Joel Hutton 2018-01-10 16:06:07 +00:00 • committed by Dimitris Papastamos
parent c84b6cb1aa
commit 46e8870385
2 changed files with 63 additions and 0 deletions
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29
include/lib/cpus/aarch64/cortex_helios.h Normal file
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/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __CORTEX_HELIOS_H__
#define __CORTEX_HELIOS_H__
#define CORTEX_HELIOS_MIDR U(0x410FD060)
/*******************************************************************************
* CPU Extended Control register specific definitions.
******************************************************************************/
#define CORTEX_HELIOS_ECTLR_EL1 S3_0_C15_C1_4
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
#define CORTEX_HELIOS_CPUACTLR_EL1 S3_0_C15_C1_0
/*******************************************************************************
* CPU Power Control register specific definitions.
******************************************************************************/
#define CORTEX_HELIOS_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define CORTEX_HELIOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0)
#endif /* __CORTEX_HELIOS_H__ */

34
lib/cpus/aarch64/cortex_helios.S Normal file
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/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
#include <bl_common.h>
#include <cortex_helios.h>
#include <cpu_macros.S>
#include <debug.h>
#include <plat_macros.S>
func cortex_helios_cpu_pwr_dwn
mrs x0, CORTEX_HELIOS_CPUPWRCTLR_EL1
orr x0, x0, #CORTEX_HELIOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
msr CORTEX_HELIOS_CPUPWRCTLR_EL1, x0
isb
ret
endfunc cortex_helios_cpu_pwr_dwn
.section .rodata.cortex_helios_regs, "aS"
cortex_helios_regs: /* The ascii list of register names to be reported */
.asciz "cpuectlr_el1", ""
func cortex_helios_cpu_reg_dump
adr x6, cortex_helios_regs
mrs x8, CORTEX_HELIOS_ECTLR_EL1
ret
endfunc cortex_helios_cpu_reg_dump
declare_cpu_ops cortex_helios, CORTEX_HELIOS_MIDR, \
CPU_NO_RESET_FUNC, \
cortex_helios_cpu_pwr_dwn