From 463b5b4a46552887c4fb70536d20f315f889add1 Mon Sep 17 00:00:00 2001 From: Govindraj Raja Date: Tue, 21 Jan 2025 12:32:14 -0600 Subject: [PATCH] fix(cpus): workaround for Cortex-A710 erratum 3701772 Cortex-A710 erratum 3701772 that applies to all revisions <= r2p1 and is still Open. The workaround is for EL3 software that performs context save/restore on a change of Security state to use a value of SCR_EL3.NS when accessing ICH_VMCR_EL2 that reflects the Security state that owns the data being saved or restored. SDEN documentation: https://developer.arm.com/documentation/SDEN-1775101/latest/ Change-Id: I997c9cfaa75321f22b4f690c4d3f234c0b51c670 Signed-off-by: Govindraj Raja --- docs/design/cpu-specific-build-macros.rst | 4 ++++ include/lib/cpus/aarch64/cortex_a710.h | 6 +++++- lib/cpus/aarch64/cortex_a710.S | 8 +++++++- lib/cpus/cpu-ops.mk | 5 +++++ lib/cpus/errata_common.c | 8 ++++++++ 5 files changed, 29 insertions(+), 2 deletions(-) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 17b295451..ed0988555 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -653,6 +653,10 @@ For Cortex-A710, the following errata build flags are defined : CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the CPU and is still open. +- ``ERRATA_A710_3701772``: This applies errata 3701772 workaround to Cortex-A710 + CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0, r2p1 of the + CPU and is still open. + For Neoverse N2, the following errata build flags are defined : - ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2 diff --git a/include/lib/cpus/aarch64/cortex_a710.h b/include/lib/cpus/aarch64/cortex_a710.h index 9df8d471b..650193cc0 100644 --- a/include/lib/cpus/aarch64/cortex_a710.h +++ b/include/lib/cpus/aarch64/cortex_a710.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023, Arm Limited. All rights reserved. + * Copyright (c) 2021-2025, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -67,4 +67,8 @@ #define CORTEX_A710_CPUPOR_EL3 S3_6_C15_C8_2 #define CORTEX_A710_CPUPMR_EL3 S3_6_C15_C8_3 +#ifndef __ASSEMBLER__ +long check_erratum_cortex_a710_3701772(long cpu_rev); +#endif /* __ASSEMBLER__ */ + #endif /* CORTEX_A710_H */ diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S index dce9c7354..71ed6dbd4 100644 --- a/lib/cpus/aarch64/cortex_a710.S +++ b/lib/cpus/aarch64/cortex_a710.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2024, Arm Limited. All rights reserved. + * Copyright (c) 2021-2025, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -22,6 +22,8 @@ #error "Cortex A710 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif +.global check_erratum_cortex_a710_3701772 + #if WORKAROUND_CVE_2022_23960 wa_cve_2022_23960_bhb_vector_table CORTEX_A710_BHB_LOOP_COUNT, cortex_a710 #endif /* WORKAROUND_CVE_2022_23960 */ @@ -218,6 +220,10 @@ workaround_reset_end cortex_a710, CVE(2022, 23960) check_erratum_chosen cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 +add_erratum_entry cortex_a710, ERRATUM(3701772), ERRATA_A710_3701772, NO_APPLY_AT_RESET + +check_erratum_ls cortex_a710, ERRATUM(3701772), CPU_REV(2, 1) + /* ---------------------------------------------------- * HW will do the cache maintenance while powering down * ---------------------------------------------------- diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 19846890d..81ce13108 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -642,6 +642,11 @@ CPU_FLAG_LIST += ERRATA_A710_2768515 # open. CPU_FLAG_LIST += ERRATA_A710_2778471 +# Flag to apply erratum 3701772 workaround during context save/restore of +# ICH_VMCR_EL2 reg. This erratum applies to revisions r0p0, r1p0, r2p0, r2p1 +# of the Cortex-A710 cpu and is still open. +CPU_FLAG_LIST += ERRATA_A710_3701772 + # Flag to apply erratum 2002655 workaround during reset. This erratum applies # to revisions r0p0 of the Neoverse-N2 cpu and is fixed in r0p1. CPU_FLAG_LIST += ERRATA_N2_2002655 diff --git a/lib/cpus/errata_common.c b/lib/cpus/errata_common.c index 4cd105e34..7c4db4648 100644 --- a/lib/cpus/errata_common.c +++ b/lib/cpus/errata_common.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -44,6 +45,13 @@ bool errata_a75_764081_applies(void) bool errata_ich_vmcr_el2_applies(void) { switch (EXTRACT_PARTNUM(read_midr())) { +#if ERRATA_A710_3701772 + case EXTRACT_PARTNUM(CORTEX_A710_MIDR): + if (check_erratum_cortex_a710_3701772(cpu_get_rev_var()) == ERRATA_APPLIES) + return true; + break; +#endif /* ERRATA_A710_3701772 */ + default: break; }