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Cortex-A57: Implement workaround for erratum 859972
Erratum 855972 applies to revision r1p3 or earlier Cortex-A57 CPUs. The recommended workaround is to disable instruction prefetch. Change-Id: I56eeac0b753eb1432bd940083372ad6f7e93b16a Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
This commit is contained in:
Eleanor Bonnici
Jeenu Viswambharan
parent
5457874575
commit
45b52c202f
6 changed files with 79 additions and 2 deletions
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@ -30,7 +30,8 @@ errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor nam
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is for example ``A57`` for the ``Cortex_A57`` CPU.
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Refer to the section *CPU errata status reporting* in
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`Firmware Design guide`_ for information on to write errata workaround functions.
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`Firmware Design guide`_ for information on how to write errata workaround
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functions.
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All workarounds are disabled by default. The platform is responsible for
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enabling these workarounds according to its requirement by defining the
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@ -98,6 +99,9 @@ For Cortex-A57, following errata build flags are defined :
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- ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57
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CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
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- ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57
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CPU. This needs to be enabled only for revision <= r1p3 of the CPU.
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CPU Specific optimizations
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--------------------------
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@ -131,7 +135,7 @@ architecture that can be enabled by the platform as desired.
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*Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.*
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.. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html
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.. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/Cortex_A53_MPCore_Software_Developers_Errata_Notice.pdf
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.. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/cortex_a57_mpcore_software_developers_errata_notice.pdf
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.. _Firmware Design guide: firmware-design.rst
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.. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf
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@ -49,6 +49,7 @@
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#define CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49)
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#define CORTEX_A57_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44)
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#define CORTEX_A57_CPUACTLR_FORCE_FPSCR_FLUSH (ULL(1) << 38)
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#define CORTEX_A57_CPUACTLR_DIS_INSTR_PREFETCH (ULL(1) << 32)
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#define CORTEX_A57_CPUACTLR_DIS_STREAMING (ULL(3) << 27)
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#define CORTEX_A57_CPUACTLR_DIS_L1_STREAMING (ULL(3) << 25)
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#define CORTEX_A57_CPUACTLR_DIS_INDIRECT_PREDICTOR (ULL(1) << 4)
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@ -49,6 +49,7 @@
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#define CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49)
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#define CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44)
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#define CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH (ULL(1) << 38)
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#define CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32)
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#define CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING (ULL(3) << 27)
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#define CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING (ULL(3) << 25)
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#define CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR (ULL(1) << 4)
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@ -306,6 +306,32 @@ func check_errata_833471
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b cpu_rev_var_ls
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endfunc check_errata_833471
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/* ---------------------------------------------------
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* Errata Workaround for Cortex A57 Errata #859972.
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* This applies only to revision <= r1p3 of Cortex A57.
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* Inputs:
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* r0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: r0-r3
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* ---------------------------------------------------
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*/
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func errata_a57_859972_wa
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mov r2, lr
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bl check_errata_859972
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mov lr, r2
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cmp r0, #ERRATA_NOT_APPLIES
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beq 1f
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ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
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orr64_imm r1, r1, CORTEX_A57_CPUACTLR_DIS_INSTR_PREFETCH
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stcopr16 r0, r1, CORTEX_A57_CPUACTLR
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1:
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bx lr
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endfunc errata_a57_859972_wa
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func check_errata_859972
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mov r1, #0x13
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b cpu_rev_var_ls
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endfunc check_errata_859972
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A57.
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* Shall clobber: r0-r6
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@ -356,6 +382,11 @@ func cortex_a57_reset_func
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bl errata_a57_833471_wa
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#endif
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#if ERRATA_A57_859972
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mov r0, r4
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bl errata_a57_859972_wa
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#endif
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/* ---------------------------------------------
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* Enable the SMP bit.
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* ---------------------------------------------
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@ -487,6 +518,7 @@ func cortex_a57_errata_report
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report_errata ERRATA_A57_828024, cortex_a57, 828024
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report_errata ERRATA_A57_829520, cortex_a57, 829520
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report_errata ERRATA_A57_833471, cortex_a57, 833471
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report_errata ERRATA_A57_859972, cortex_a57, 859972
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pop {r12, lr}
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bx lr
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@ -304,6 +304,30 @@ func check_errata_833471
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b cpu_rev_var_ls
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endfunc check_errata_833471
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/* --------------------------------------------------
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* Errata Workaround for Cortex A57 Errata #859972.
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* This applies only to revision <= r1p3 of Cortex A57.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber:
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* --------------------------------------------------
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*/
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func errata_a57_859972_wa
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mov x17, x30
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bl check_errata_859972
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cbz x0, 1f
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mrs x1, CORTEX_A57_CPUACTLR_EL1
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orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH
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msr CORTEX_A57_CPUACTLR_EL1, x1
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1:
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ret x17
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endfunc errata_a57_859972_wa
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func check_errata_859972
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mov x1, #0x13
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b cpu_rev_var_ls
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endfunc check_errata_859972
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A57.
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* Shall clobber: x0-x19
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@ -354,6 +378,11 @@ func cortex_a57_reset_func
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bl errata_a57_833471_wa
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#endif
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#if ERRATA_A57_859972
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mov x0, x18
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bl errata_a57_859972_wa
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#endif
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/* ---------------------------------------------
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* Enable the SMP bit.
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* ---------------------------------------------
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@ -483,6 +512,8 @@ func cortex_a57_errata_report
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report_errata ERRATA_A57_828024, cortex_a57, 828024
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report_errata ERRATA_A57_829520, cortex_a57, 829520
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report_errata ERRATA_A57_833471, cortex_a57, 833471
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report_errata ERRATA_A57_859972, cortex_a57, 859972
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ldp x8, x30, [sp], #16
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ret
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@ -91,6 +91,10 @@ ERRATA_A57_829520 ?=0
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# only to revision <= r1p2 of the Cortex A57 cpu.
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ERRATA_A57_833471 ?=0
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# Flag to apply erratum 855972 workaround during reset. This erratum applies
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# only to revision <= r1p3 of the Cortex A57 cpu.
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ERRATA_A57_859972 ?=0
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# Process ERRATA_A53_826319 flag
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$(eval $(call assert_boolean,ERRATA_A53_826319))
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$(eval $(call add_define,ERRATA_A53_826319))
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@ -143,6 +147,10 @@ $(eval $(call add_define,ERRATA_A57_829520))
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$(eval $(call assert_boolean,ERRATA_A57_833471))
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$(eval $(call add_define,ERRATA_A57_833471))
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# Process ERRATA_A57_859972 flag
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$(eval $(call assert_boolean,ERRATA_A57_859972))
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$(eval $(call add_define,ERRATA_A57_859972))
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# Errata build flags
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ifneq (${ERRATA_A53_843419},0)
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TF_LDFLAGS_aarch64 += --fix-cortex-a53-843419
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