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Merge "plat/arm: Introduce corstone700 platform." into integration

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Paul Beesley 2019-08-20 14:47:56 +00:00 • committed by TrustedFirmware Code Review
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147
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/*
* Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/dts-v1/;
/ {
model = "corstone700";
compatible = "arm,Corstone-700";
interrupt-parent = <&gic>;
#address-cells = <1>;
#size-cells = <1>;
chosen {
bootargs = "console=ttyAMA0 root=/dev/vda2 rw loglevel=9";
linux,initrd-start = <0x02a00000>;
linux,initrd-end = <0x04000000>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0>;
next-level-cache = <&L2_0>;
};
};
memory@2000000 {
device_type = "memory";
reg = <0x02000000 0x02000000>;
};
gic: interrupt-controller@1c000000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x1c010000 0x1000>,
<0x1c02f000 0x2000>,
<0x1c04f000 0x1000>,
<0x1c06f000 0x2000>;
interrupts = <1 9 0xf08>;
};
L2_0: l2-cache0 {
compatible = "cache";
};
refclk100mhz: refclk100mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "apb_pclk";
};
smbclk: refclk24mhzx2 {
/* Reference 24MHz clock x 2 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
clock-output-names = "smclk";
};
serial0: uart@1a510000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x1a510000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 19 4>;
clocks = <&refclk100mhz>, <&smbclk>;
clock-names = "apb_pclk", "smclk";
};
serial1: uart@1a520000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x1a520000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 20 4>;
clocks = <&refclk100mhz>, <&smbclk>;
clock-names = "apb_pclk", "smclk";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 0xf08>,
<1 14 0xf08>,
<1 11 0xf08>,
<1 10 0xf08>;
};
mbox_es0mhu0: mhu@1b000000 {
compatible = "arm,mhuv2","arm,primecell";
reg = <0x1b000000 0x1000>,
<0x1b010000 0x1000>;
clocks = <&refclk100mhz>;
clock-names = "apb_pclk";
interrupts = <0 12 4>;
interrupt-names = "mhu_rx";
#mbox-cells = <1>;
mbox-name = "arm-es0-mhu0";
};
mbox_es0mhu1: mhu@1b020000 {
compatible = "arm,mhuv2","arm,primecell";
reg = <0x1b020000 0x1000>,
<0x1b030000 0x1000>;
clocks = <&refclk100mhz>;
clock-names = "apb_pclk";
interrupts = <0 47 4>;
interrupt-names = "mhu_rx";
#mbox-cells = <1>;
mbox-name = "arm-es0-mhu1";
};
mbox_semhu1: mhu@1b820000 {
compatible = "arm,mhuv2","arm,primecell";
reg = <0x1b820000 0x1000>,
<0x1b830000 0x1000>;
clocks = <&refclk100mhz>;
clock-names = "apb_pclk";
interrupts = <0 45 4>;
interrupt-names = "mhu_rx";
#mbox-cells = <1>;
mbox-name = "arm-se-mhu1";
};
client {
compatible = "arm,client";
mboxes = <&mbox_es0mhu0 0>, <&mbox_es0mhu1 0>, <&mbox_semhu1 0>;
mbox-names = "es0mhu0", "es0mhu1", "semhu1";
};
extsys0: extsys@1A010310 {
compatible = "arm,extsys_ctrl";
reg = <0x1A010310 0x4>,
<0x1A010314 0x4>;
reg-names = "rstreg", "streg";
};
};

100
plat/arm/board/corstone700/corstone700_helpers.S Normal file
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/*
* Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
#include <platform_def.h>
.globl plat_secondary_cold_boot_setup
.globl plat_get_my_entrypoint
.globl plat_is_my_cpu_primary
.globl plat_arm_calc_core_pos
/* --------------------------------------------------------------------
* void plat_secondary_cold_boot_setup (void);
*
* For AArch32, cold-booting secondary CPUs is not yet
* implemented and they panic.
* --------------------------------------------------------------------
*/
func plat_secondary_cold_boot_setup
cb_panic:
b cb_panic
endfunc plat_secondary_cold_boot_setup
/* ---------------------------------------------------------------------
* unsigned long plat_get_my_entrypoint (void);
*
* Main job of this routine is to distinguish between a cold and warm
* boot. On Corstone700, this information can be queried from the power
* controller. The Power Control SYS Status Register (PSYSR) indicates
* the wake-up reason for the CPU.
*
* For a cold boot, return 0.
* For a warm boot, Not yet supported.
*
* TODO: PSYSR is a common register and should be
* accessed using locks. Since it is not possible
* to use locks immediately after a cold reset
* we are relying on the fact that after a cold
* reset all cpus will read the same WK field
* ---------------------------------------------------------------------
*/
func plat_get_my_entrypoint
/* TODO support warm boot */
/* Cold reset */
mov r0, #0
bx lr
endfunc plat_get_my_entrypoint
/* -----------------------------------------------------
* unsigned int plat_is_my_cpu_primary (void);
*
* Find out whether the current CPU is the primary
* CPU.
* -----------------------------------------------------
*/
func plat_is_my_cpu_primary
ldcopr r0, MPIDR
ldr r1, =MPIDR_AFFINITY_MASK
and r0, r1
cmp r0, #0
moveq r0, #1
movne r0, #0
bx lr
endfunc plat_is_my_cpu_primary
/* ---------------------------------------------------------------------
* unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
*
* Function to calculate the core position on Corstone700.
*
* (ClusterId * MAX_CPUS_PER_CLUSTER * MAX_PE_PER_CPU) +
* (CPUId * MAX_PE_PER_CPU) +
* ThreadId
*
* which can be simplified as:
*
* ((ClusterId * MAX_CPUS_PER_CLUSTER + CPUId) * MAX_PE_PER_CPU)
* + ThreadId
* ---------------------------------------------------------------------
*/
func plat_arm_calc_core_pos
mov r3, r0
/* Extract individual affinity fields from MPIDR */
ubfx r0, r3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
ubfx r1, r3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
ubfx r2, r3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
/* Compute linear position */
mov r3, #CORSTONE700_MAX_CPUS_PER_CLUSTER
mla r1, r2, r3, r1
mov r3, #CORSTONE700_MAX_PE_PER_CPU
mla r0, r1, r3, r0
bx lr
endfunc plat_arm_calc_core_pos

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plat/arm/board/corstone700/corstone700_plat.c Normal file
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/*
* Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/bl_common.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
#include <platform_def.h>
/*
* Table of regions to map using the MMU.
* Replace or extend the below regions as required
*/
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
ARM_MAP_NS_DRAM1,
CORSTONE700_MAP_DEVICE,
{0}
};
/* Corstone700 only has one always-on power domain and there
* is no power control present
*/
void __init plat_arm_pwrc_setup(void)
{
}
unsigned int plat_get_syscnt_freq2(void)
{
return CORSTONE700_TIMER_BASE_FREQUENCY;
}

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/*
* Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <lib/psci/psci.h>
#include <plat/arm/common/plat_arm.h>
/*******************************************************************************
* Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
* platform layer will take care of registering the handlers with PSCI.
******************************************************************************/
plat_psci_ops_t plat_arm_psci_pm_ops = {
/* dummy struct */
.validate_ns_entrypoint = NULL
};
const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
{
return ops;
}

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/*
* Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* We assume that all security programming is done by the primary core.
*/
void plat_arm_security_setup(void)
{
/*
* If the platform had additional peripheral specific security
* configurations, those would be configured here.
*/
}

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/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
/* The Corstone700 power domain tree descriptor */
static unsigned char corstone700_power_domain_tree_desc
[PLAT_ARM_CLUSTER_COUNT + 2];
/*******************************************************************************
* This function dynamically constructs the topology according to
* CLUSTER_COUNT and returns it.
******************************************************************************/
const unsigned char *plat_get_power_domain_tree_desc(void)
{
int i;
/*
* The highest level is the system level. The next level is constituted
* by clusters and then cores in clusters.
*/
corstone700_power_domain_tree_desc[0] = 1;
corstone700_power_domain_tree_desc[1] = PLAT_ARM_CLUSTER_COUNT;
for (i = 0; i < PLAT_ARM_CLUSTER_COUNT; i++)
corstone700_power_domain_tree_desc[i + 2] = PLATFORM_CORE_COUNT;
return corstone700_power_domain_tree_desc;
}
/******************************************************************************
* This function implements a part of the critical interface between the PSCI
* generic layer and the platform that allows the former to query the platform
* to convert an MPIDR to a unique linear index. An error code (-1) is
* returned in case the MPIDR is invalid.
*****************************************************************************/
int plat_core_pos_by_mpidr(u_register_t mpidr)
{
return plat_arm_calc_core_pos(mpidr);
}

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/*
* Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PLATFORM_DEF_H
#define PLATFORM_DEF_H
#include <lib/utils_def.h>
#include <lib/xlat_tables/xlat_tables_defs.h>
#include <plat/arm/board/common/v2m_def.h>
#include <plat/arm/common/arm_spm_def.h>
#include <plat/common/common_def.h>
/* Core/Cluster/Thread counts for Corstone700 */
#define CORSTONE700_CLUSTER_COUNT 1
#define CORSTONE700_MAX_CPUS_PER_CLUSTER 4
#define CORSTONE700_MAX_PE_PER_CPU 1
#define CORSTONE700_CORE_COUNT (CORSTONE700_CLUSTER_COUNT * \
CORSTONE700_MAX_CPUS_PER_CLUSTER * \
CORSTONE700_MAX_PE_PER_CPU)
#define PLATFORM_CORE_COUNT CORSTONE700_CORE_COUNT
#define PLAT_ARM_CLUSTER_COUNT CORSTONE700_CLUSTER_COUNT
/* UART related constants */
#define PLAT_ARM_BOOT_UART_BASE 0x1a510000
#define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ
#define PLAT_ARM_RUN_UART_BASE 0x1a520000
#define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ
#define ARM_CONSOLE_BAUDRATE 115200
#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE
#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ
/* Memory related constants */
#define ARM_DRAM1_BASE UL(0x80000000)
#define ARM_DRAM1_SIZE UL(0x80000000)
#define ARM_DRAM1_END (ARM_DRAM1_BASE + \
ARM_DRAM1_SIZE - 1)
#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE
#define ARM_NS_DRAM1_SIZE ARM_DRAM1_SIZE
#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \
ARM_NS_DRAM1_SIZE - 1)
#define ARM_TRUSTED_SRAM_BASE UL(0x02000000)
#define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE
#define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */
#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */
/* The remaining Trusted SRAM is used to load the BL images */
#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \
ARM_SHARED_RAM_SIZE)
#define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \
ARM_SHARED_RAM_SIZE)
/*
* SP_MIN is the only BL image in SRAM. Allocate the whole of SRAM (excluding
* the page reserved for fw_configs) to BL32
*/
#define BL32_BASE (ARM_BL_RAM_BASE + PAGE_SIZE)
#define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
/*
* Some data must be aligned on the biggest cache line size in the platform.
* This is known only to the platform as it might have a combination of
* integrated and external caches.
*/
#define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT)
#define ARM_CACHE_WRITEBACK_SHIFT 6
/*
* To enable TB_FW_CONFIG to be loaded by BL1, define the corresponding base
* and limit. Leave enough space for BL2 meminfo.
*/
#define ARM_TB_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t))
#define ARM_TB_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE / 2U))
/*
* The max number of regions like RO(code), coherent and data required by
* different BL stages which need to be mapped in the MMU.
*/
#define ARM_BL_REGIONS 2
#define PLAT_ARM_MMAP_ENTRIES 8
#define MAX_XLAT_TABLES 5
#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \
ARM_BL_REGIONS)
/* GIC related constants */
#define PLAT_ARM_GICD_BASE 0x1C010000
#define PLAT_ARM_GICC_BASE 0x1C02F000
/* Timer/watchdog related constants */
#define ARM_SYS_CNTCTL_BASE UL(0x1a200000)
#define ARM_SYS_CNTREAD_BASE UL(0x1a210000)
#define ARM_SYS_TIMCTL_BASE UL(0x1a220000)
#define CORSTONE700_TIMER_BASE_FREQUENCY UL(24000000)
#define CORSTONE700_IRQ_TZ_WDOG 32
#define CORSTONE700_IRQ_SEC_SYS_TIMER 34
#define PLAT_MAX_PWR_LVL 2
/*
* Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The
* power levels have a 1:1 mapping with the MPIDR affinity levels.
*/
#define ARM_PWR_LVL0 MPIDR_AFFLVL0
#define ARM_PWR_LVL1 MPIDR_AFFLVL1
#define ARM_PWR_LVL2 MPIDR_AFFLVL2
/*
* Macros for local power states in ARM platforms encoded by State-ID field
* within the power-state parameter.
*/
/* Local power state for power domains in Run state. */
#define ARM_LOCAL_STATE_RUN U(0)
/* Local power state for retention. Valid only for CPU power domains */
#define ARM_LOCAL_STATE_RET U(1)
/* Local power state for OFF/power-down. Valid for CPU and cluster
* power domains
*/
#define ARM_LOCAL_STATE_OFF U(2)
#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE
#define PLAT_ARM_NSTIMER_FRAME_ID U(1)
#define PLAT_ARM_NS_IMAGE_OFFSET (ARM_DRAM1_BASE + UL(0x8000000))
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
/*
* This macro defines the deepest retention state possible. A higher state
* ID will represent an invalid or a power down state.
*/
#define PLAT_MAX_RET_STATE 1
/*
* This macro defines the deepest power down states possible. Any state ID
* higher than this is invalid.
*/
#define PLAT_MAX_OFF_STATE 2
#define PLATFORM_STACK_SIZE UL(0x440)
#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \
ARM_SHARED_RAM_BASE, \
ARM_SHARED_RAM_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \
ARM_NS_DRAM1_BASE, \
ARM_NS_DRAM1_SIZE, \
MT_MEMORY | MT_RW | MT_NS)
#define ARM_MAP_BL_RO MAP_REGION_FLAT( \
BL_CODE_BASE, \
BL_CODE_END \
- BL_CODE_BASE, \
MT_CODE | MT_SECURE), \
MAP_REGION_FLAT( \
BL_RO_DATA_BASE, \
BL_RO_DATA_END \
- BL_RO_DATA_BASE, \
MT_RO_DATA | MT_SECURE)
#if USE_COHERENT_MEM
#define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \
BL_COHERENT_RAM_BASE, \
BL_COHERENT_RAM_END \
- BL_COHERENT_RAM_BASE, \
MT_DEVICE | MT_RW | MT_SECURE)
#endif
#define CORSTONE700_DEVICE_BASE (0x1A000000)
#define CORSTONE700_DEVICE_SIZE (0x26000000)
#define CORSTONE700_MAP_DEVICE MAP_REGION_FLAT( \
CORSTONE700_DEVICE_BASE, \
CORSTONE700_DEVICE_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
#define ARM_IRQ_SEC_PHY_TIMER 29
#define ARM_IRQ_SEC_SGI_0 8
#define ARM_IRQ_SEC_SGI_1 9
#define ARM_IRQ_SEC_SGI_2 10
#define ARM_IRQ_SEC_SGI_3 11
#define ARM_IRQ_SEC_SGI_4 12
#define ARM_IRQ_SEC_SGI_5 13
#define ARM_IRQ_SEC_SGI_6 14
#define ARM_IRQ_SEC_SGI_7 15
/*
* Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3
* terminology. On a GICv2 system or mode, the lists will be merged and treated
* as Group 0 interrupts.
*/
#define ARM_G1S_IRQ_PROPS(grp) \
INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
(grp), GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \
(grp), GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \
(grp), GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \
(grp), GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \
(grp), GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \
(grp), GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \
(grp), GIC_INTR_CFG_EDGE)
#define ARM_G0_IRQ_PROPS(grp) \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \
GIC_INTR_CFG_EDGE)
/*
* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
* terminology. On a GICv2 system or mode, the lists will be merged and treated
* as Group 0 interrupts.
*/
#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
ARM_G1S_IRQ_PROPS(grp), \
INTR_PROP_DESC(CORSTONE700_IRQ_TZ_WDOG, \
GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(CORSTONE700_IRQ_SEC_SYS_TIMER, \
GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL) \
#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
#endif /* PLATFORM_DEF_H */

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#
# Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
CORSTONE700_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S
BL32_SOURCES += plat/arm/common/aarch32/arm_helpers.S \
plat/arm/common/arm_console.c \
plat/arm/common/arm_common.c \
lib/xlat_tables/aarch32/xlat_tables.c \
lib/xlat_tables/xlat_tables_common.c \
${CORSTONE700_CPU_LIBS}
PLAT_INCLUDES := -Iplat/arm/board/corstone700/include
NEED_BL32 := yes
CORSTONE700_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v2/gicv2_main.c \
drivers/arm/gic/v2/gicv2_helpers.c \
plat/common/plat_gicv2.c \
plat/arm/common/arm_gicv2.c
# BL1/BL2 Image not a part of the capsule Image for Corstone700
override NEED_BL1 := no
override NEED_BL2 := no
override NEED_BL2U := no
#TFA for Corstone700 starts from BL32
override RESET_TO_SP_MIN := 1
#Device tree
CORSTONE700_HW_CONFIG_DTS := fdts/corstone700.dts
CORSTONE700_HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb
FDT_SOURCES += ${CORSTONE700_HW_CONFIG_DTS}
$(eval CORSTONE700_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(CORSTONE700_HW_CONFIG_DTS)))
# Add the HW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${CORSTONE700_HW_CONFIG},--hw-config))
# Check for Linux kernel as a BL33 image by default
$(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33))
ifndef ARM_PRELOADED_DTB_BASE
$(error "ARM_PRELOADED_DTB_BASE must be set if ARM_LINUX_KERNEL_AS_BL33 is used.")
endif
$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
include plat/arm/board/common/board_common.mk

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/*
* Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <plat/arm/common/plat_arm.h>
void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
}

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#
# Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
# SP_MIN source files specific to FVP platform
BL32_SOURCES += drivers/cfi/v2m/v2m_flash.c \
lib/utils/mem_region.c \
plat/arm/board/corstone700/corstone700_helpers.S \
plat/arm/board/corstone700/corstone700_topology.c \
plat/arm/board/corstone700/corstone700_security.c \
plat/arm/board/corstone700/corstone700_plat.c \
plat/arm/board/corstone700/corstone700_pm.c \
plat/arm/board/corstone700/sp_min/corstone700_sp_min_setup.c \
${CORSTONE700_GIC_SOURCES}
include plat/arm/common/sp_min/arm_sp_min.mk