mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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fix(intel): redesign F2SOC bridge enable and disable flow for Agilex5
This is to redesign the flow of F2SOC bridge enable and disable. Change-Id: I9b2a2a11fa2ad8e622765971fdf59a0738246e13 Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
This commit is contained in:
Sieu Mun Tang
parent
5b9e703537
commit
42e906205e
1 changed files with 113 additions and 122 deletions
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@ -404,10 +404,11 @@ int socfpga_bridges_enable(uint32_t mask)
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uint32_t brg_lst = 0;
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#endif
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/**************** SOC2FPGA ****************/
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/* Enable s2f bridge */
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socfpga_s2f_bridge_mask(mask, &brg_mask, &noc_mask);
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#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
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/**************** SOC2FPGA ****************/
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brg_lst = mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST));
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if ((brg_mask & RSTMGR_BRGMODRSTMASK_SOC2FPGA)
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&& ((brg_lst & RSTMGR_BRGMODRSTMASK_SOC2FPGA) != 0)) {
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@ -593,6 +594,8 @@ int socfpga_bridges_enable(uint32_t mask)
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}
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#endif
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/**************** FPGA2SOC ****************/
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/* Enable f2s bridge */
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socfpga_f2s_bridge_mask(mask, &brg_mask, &f2s_idlereq,
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&f2s_force_drain, &f2s_en,
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@ -603,89 +606,28 @@ int socfpga_bridges_enable(uint32_t mask)
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if ((brg_mask & RSTMGR_BRGMODRSTMASK_FPGA2SOC)
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&& ((brg_lst & RSTMGR_BRGMODRSTMASK_FPGA2SOC) != 0)) {
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/*
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* To request handshake
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* Write Reset Manager hdsken[fpgahsen] = 1
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* To deassert reset
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* Write Reset Manager brgmodrst[fpga2soc] = 0
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*/
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VERBOSE("Set FPGA hdsken(fpgahsen) ...\n");
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mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_FPGAHSEN);
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VERBOSE("Deassert F2S ...\n");
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mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST),
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RSTMGR_BRGMODRST_FPGA2SOC);
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/*
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* To request handshake
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* Write Reset Manager hdskreq[fpgahsreq] = 1
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* To clear handshake fpgahsack
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* Write Reset Manager hdskreq[fpgahsack] = 1
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*/
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VERBOSE("Set FPGA hdskreq(fpgahsreq) ...\n");
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mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
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/*
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* To poll idle status
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* Read Reset Manager hdskack[fpgahsack] = 1
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*/
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VERBOSE("Get FPGA hdskack(fpgahsack) ...\n");
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if ((mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST))
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& RSTMGR_BRGMODRST_FPGA2SOC) == 0x00) {
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ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
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RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK,
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300);
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}
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if (ret < 0) {
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ERROR("FPGA bridge fpga handshake fpgahsreq: Timeout\n");
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}
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/*
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* To fence and drain traffic
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* Write Reset Manager hdskreq[f2s_flush_req] = 1
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*/
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VERBOSE("Set F2S hdskreq(f2s_flush_req) ...\n");
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mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
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RSTMGR_HDSKREQ_FPGA2SOCREQ);
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/*
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* To poll idle status
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* Read Reset Manager hdskack[f2s_flush_ack] = 1
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*/
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VERBOSE("Get F2S hdskack(f2s_flush_ack) ...\n");
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if ((mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST))
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& RSTMGR_BRGMODRST_FPGA2SOC) == 0x00) {
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ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
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RSTMGR_HDSKACK_FPGA2SOCACK, RSTMGR_HDSKACK_FPGA2SOCACK,
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300);
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}
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if (ret < 0) {
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ERROR("F2S bridge fpga handshake f2sdram_flush_req: Timeout\n");
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}
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VERBOSE("Clear FPGA hdskack(fpgahsack) ...\n");
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mmio_setbits_32(SOCFPGA_RSTMGR(HDSKACK),
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RSTMGR_HDSKACK_FPGAHSACK);
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/*
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* To clear idle request
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* Write Reset Manager hdskreq[fpgahsreq] = 1
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* Write Reset Manager hdskreq[fpgahsreq] = 0
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*/
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VERBOSE("Clear FPGA hdskreq(fpgahsreq) ...\n");
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mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
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/*
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* To clear idle request
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* Write Reset Manager hdskreq[f2s_flush_req] = 1
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*/
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VERBOSE("Clear F2S hdskreq(f2s_flush_req) ...\n");
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mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
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RSTMGR_HDSKREQ_FPGA2SOCREQ);
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/*
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* To poll idle status
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* Read Reset Manager hdskack[f2s_flush_ack] = 0
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*/
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VERBOSE("Get F2SDRAM hdskack(f2s_flush_ack) ...\n");
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if ((mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST))
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& RSTMGR_BRGMODRST_FPGA2SOC) == 0x00) {
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ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
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RSTMGR_HDSKACK_FPGA2SOCACK, RSTMGR_HDSKACK_FPGA2SOCACK_DASRT,
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300);
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}
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if (ret < 0) {
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ERROR("F2S bridge fpga handshake f2s_flush_ack: Timeout\n");
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}
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RSTMGR_HDSKACK_FPGAHSREQ);
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/*
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* To poll idle status
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@ -695,8 +637,9 @@ int socfpga_bridges_enable(uint32_t mask)
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if ((mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST))
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& RSTMGR_BRGMODRST_FPGA2SOC) == 0x00) {
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ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
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RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK_DASRT,
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300);
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RSTMGR_HDSKACK_FPGAHSACK,
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RSTMGR_HDSKACK_FPGAHSACK_DASRT,
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1000);
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}
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if (ret < 0) {
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@ -704,27 +647,46 @@ int socfpga_bridges_enable(uint32_t mask)
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}
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/*
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* To assert reset
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* Write Reset Manager brgmodrst[fpga2soc] = 1
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* To clear handshake f2s_flush_ack
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* Write Reset Manager hdskreq[f2s_flush_ack] = 1
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*/
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VERBOSE("Assert F2S ...\n");
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mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), RSTMGR_BRGMODRST_FPGA2SOC);
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udelay(1000);
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VERBOSE("Clear F2S hdskack(f2s_flush_ack) ...\n");
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mmio_setbits_32(SOCFPGA_RSTMGR(HDSKACK),
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RSTMGR_HDSKACK_F2S_FLUSH);
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/*
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* To deassert reset
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* Write Reset Manager brgmodrst[fpga2soc] = 0
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* To clear idle request
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* Write Reset Manager hdskreq[f2s_flush_req] = 0
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*/
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VERBOSE("Deassert F2S ...\n");
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mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), RSTMGR_BRGMODRST_FPGA2SOC);
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VERBOSE("Clear F2S hdskreq(f2s_flush_req) ...\n");
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mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
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RSTMGR_HDSKREQ_F2S_FLUSH);
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/* Write System Manager f2s bridge control register[f2soc_enable] = 1 */
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/*
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* To poll idle status
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* Read Reset Manager hdskack[f2s_flush_ack] = 0
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*/
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VERBOSE("Get F2SDRAM hdskack(f2s_flush_ack) ...\n");
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if ((mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST))
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& RSTMGR_BRGMODRST_FPGA2SOC) == 0x00) {
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ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
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RSTMGR_HDSKACK_FPGA2SOCACK,
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RSTMGR_HDSKACK_FPGA2SOCACK_DASRT,
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1000);
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}
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if (ret < 0) {
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ERROR("F2S bridge fpga handshake f2s_flush_ack: Timeout\n");
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}
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/* Write System Manager f2s_bridge_ctrl [f2soc_enable] = 1 */
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VERBOSE("Deassert F2S f2soc_enable ...\n");
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mmio_setbits_32(SOCFPGA_SYSMGR(F2S_BRIDGE_CTRL),
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SYSMGR_F2S_BRIDGE_CTRL_EN);
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}
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/**************** FPGA2SDRAM ****************/
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/* Enable FPGA2SDRAM bridge */
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if ((brg_mask & RSTMGR_BRGMODRSTMASK_F2SDRAM0)
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&& ((brg_lst & RSTMGR_BRGMODRSTMASK_F2SDRAM0) != 0)) {
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@ -932,6 +894,8 @@ int socfpga_bridges_disable(uint32_t mask)
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uint32_t f2s_respempty = 0;
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uint32_t f2s_cmdidle = 0;
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/**************** SOC2FPGA ****************/
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/* Disable s2f bridge */
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socfpga_s2f_bridge_mask(mask, &brg_mask, &noc_mask);
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#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
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@ -973,6 +937,8 @@ int socfpga_bridges_disable(uint32_t mask)
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udelay(1000);
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}
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/**************** LWSOCFPGA ****************/
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/* Disable LWSOC2FPGA bridge */
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if (brg_mask & RSTMGR_BRGMODRSTMASK_LWHPS2FPGA) {
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/*
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@ -1035,6 +1001,8 @@ int socfpga_bridges_disable(uint32_t mask)
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}
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#endif
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/**************** FPGA2SOC ****************/
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/* Disable f2s bridge */
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socfpga_f2s_bridge_mask(mask, &brg_mask, &f2s_idlereq,
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&f2s_force_drain, &f2s_en,
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@ -1042,69 +1010,92 @@ int socfpga_bridges_disable(uint32_t mask)
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#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
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/* Disable FPGA2SOC bridge */
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if (brg_mask & RSTMGR_BRGMODRSTMASK_FPGA2SOC) {
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/*
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* To request handshake
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* Write Reset Manager hdsken[f2soc_flush] = 1
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*/
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VERBOSE("Enable FPGA hdsken(f2soc_flush) ...\n");
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mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN),
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RSTMGR_HDSKEN_F2S_FLUSH);
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/*
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* To request handshake
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* Write Reset Manager hdsken[fpgahsen] = 1
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*/
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VERBOSE("Set FPGA hdsken(fpgahsen) ...\n");
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VERBOSE("Enable FPGA hdsken(fpgahsen) ...\n");
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mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_FPGAHSEN);
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/*
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* To clear handshake request
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* Write Reset Manager hdskreq[fpgahsreq] = 0
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* To clear handshake fpgahsack
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* Write Reset Manager hdskack[fpgahsack] = 1
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*/
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VERBOSE("Clear FPGA hdskreq(fpgahsreq) ...\n");
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mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
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VERBOSE("Clear FPGA hdskack(fpgahsack) ...\n");
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mmio_setbits_32(SOCFPGA_RSTMGR(HDSKACK),
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RSTMGR_HDSKACK_FPGAHSACK);
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/*
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* To clear handshake request
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* Write Reset Manager hdskreq[f2s_flush_req] = 0
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* To set handshake request
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* Write Reset Manager hdskreq[fpgahsreq] = 1
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*/
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VERBOSE("Clear F2S hdskreq(f2s_flush_req) ...\n");
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mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
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RSTMGR_HDSKREQ_FPGA2SOCREQ);
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VERBOSE("Set FPGA hdskreq(fpgahsreq) ...\n");
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mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
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RSTMGR_HDSKREQ_FPGAHSREQ);
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/*
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* To poll idle status
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* Read Reset Manager hdskack[f2s_flush_ack] = 0
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*/
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VERBOSE("Get F2SDRAM hdskack(f2s_flush_ack) ...\n");
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ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
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RSTMGR_HDSKACK_FPGA2SOCACK, RSTMGR_HDSKACK_FPGA2SOCACK_DASRT,
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300);
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if (ret < 0) {
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ERROR("F2S bridge fpga handshake f2s_flush_ack: Timeout\n");
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}
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/*
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* To poll idle status
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* Read Reset Manager hdskack[fpgahsack] = 0
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* Read Reset Manager hdskack[fpgahsack] = 1
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*/
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VERBOSE("Get FPGA hdskack(fpgahsack) ...\n");
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ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
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RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK_DASRT,
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300);
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RSTMGR_HDSKACK_FPGAHSACK,
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RSTMGR_HDSKACK_FPGAHSACK,
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1000);
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if (ret < 0) {
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ERROR("F2S bridge fpga handshake fpgahsack: Timeout\n");
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}
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/*
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* To clear handshake f2s_flush_ack
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* Write Reset Manager hdskack[f2s_flush_ack] = 1
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*/
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VERBOSE("Clear F2S hdskack(f2s_flush_ack) ...\n");
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mmio_setbits_32(SOCFPGA_RSTMGR(HDSKACK),
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RSTMGR_HDSKACK_F2S_FLUSH);
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/*
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* To set handshake request
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* Write Reset Manager hdskreq[f2s_flush_req] = 1
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*/
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VERBOSE("Set FPGA hdskreq(f2s_flush_req) ...\n");
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mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
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RSTMGR_HDSKREQ_F2S_FLUSH);
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/*
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* To poll idle status
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* Read Reset Manager hdskack[f2s_flush_ack] = 1
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*/
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VERBOSE("Get FPGA hdskack(f2s_flush_ack) ...\n");
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ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
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RSTMGR_HDSKACK_FPGA2SOCACK,
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RSTMGR_HDSKACK_F2S_FLUSH,
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1000);
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if (ret < 0) {
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ERROR("F2S bridge fpga handshake f2s_flush_ack: Timeout\n");
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}
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/*
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* To assert reset
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* Write Reset Manager brgmodrst[fpga2soc] = 1
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*/
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VERBOSE("Assert F2S ...\n");
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mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), RSTMGR_BRGMODRST_FPGA2SOC);
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udelay(1000);
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/* Write System Manager f2s bridge control register[f2soc_enable] = 0 */
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VERBOSE("Assert F2S f2soc_enable ...\n");
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mmio_clrbits_32(SOCFPGA_SYSMGR(F2S_BRIDGE_CTRL),
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SYSMGR_F2S_BRIDGE_CTRL_EN);
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mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
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RSTMGR_BRGMODRST_FPGA2SOC);
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}
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/**************** FPGA2SDRAM ****************/
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/* Disable FPGA2SDRAM bridge */
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if (brg_mask & RSTMGR_BRGMODRSTMASK_F2SDRAM0) {
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/*
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