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https://github.com/ARM-software/arm-trusted-firmware.git
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drivers: cci: Fix MISRA defects
Change-Id: Ifdb0ceec19d267b14d796b5d31f08f7342190484 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
This commit is contained in:
Antonio Nino Diaz
parent
6d5f0631a6
commit
4213e9bacd
2 changed files with 94 additions and 91 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -10,11 +10,12 @@
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#include <cci.h>
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#include <debug.h>
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#include <mmio.h>
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#include <stdbool.h>
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#include <stdint.h>
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#define MAKE_CCI_PART_NUMBER(hi, lo) ((hi << 8) | lo)
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#define CCI_PART_LO_MASK 0xff
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#define CCI_PART_HI_MASK 0xf
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#define MAKE_CCI_PART_NUMBER(hi, lo) (((hi) << 8) | (lo))
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#define CCI_PART_LO_MASK U(0xff)
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#define CCI_PART_HI_MASK U(0xf)
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/* CCI part number codes read from Peripheral ID registers 0 and 1 */
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#define CCI400_PART_NUM 0x420
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@ -32,14 +33,14 @@ static const int *cci_slave_if_map;
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static unsigned int max_master_id;
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static int cci_num_slave_ports;
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static int validate_cci_map(const int *map)
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static bool validate_cci_map(const int *map)
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{
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unsigned int valid_cci_map = 0;
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unsigned int valid_cci_map = 0U;
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int slave_if_id;
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int i;
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unsigned int i;
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/* Validate the map */
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for (i = 0; i <= max_master_id; i++) {
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for (i = 0U; i <= max_master_id; i++) {
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slave_if_id = map[i];
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if (slave_if_id < 0)
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@ -47,22 +48,22 @@ static int validate_cci_map(const int *map)
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if (slave_if_id >= cci_num_slave_ports) {
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ERROR("Slave interface ID is invalid\n");
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return 0;
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return false;
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}
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if (valid_cci_map & (1 << slave_if_id)) {
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if ((valid_cci_map & (1U << slave_if_id)) != 0U) {
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ERROR("Multiple masters are assigned same slave interface ID\n");
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return 0;
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return false;
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}
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valid_cci_map |= 1 << slave_if_id;
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valid_cci_map |= 1U << slave_if_id;
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}
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if (!valid_cci_map) {
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if (valid_cci_map == 0U) {
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ERROR("No master is assigned a valid slave interface\n");
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return 0;
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return false;
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}
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return 1;
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return true;
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}
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/*
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@ -108,8 +109,8 @@ static int get_slave_ports(unsigned int part_num)
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void cci_init(uintptr_t base, const int *map, unsigned int num_cci_masters)
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{
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assert(map);
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assert(base);
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assert(map != NULL);
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assert(base != 0U);
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cci_base = base;
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cci_slave_if_map = map;
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@ -119,7 +120,7 @@ void cci_init(uintptr_t base, const int *map, unsigned int num_cci_masters)
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* Master Id's are assigned from zero, So in an array of size n
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* the max master id is (n - 1).
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*/
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max_master_id = num_cci_masters - 1;
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max_master_id = num_cci_masters - 1U;
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cci_num_slave_ports = get_slave_ports(read_cci_part_number(base));
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#endif
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assert(cci_num_slave_ports >= 0);
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@ -133,7 +134,7 @@ void cci_enable_snoop_dvm_reqs(unsigned int master_id)
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assert(master_id <= max_master_id);
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assert((slave_if_id < cci_num_slave_ports) && (slave_if_id >= 0));
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assert(cci_base);
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assert(cci_base != 0U);
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/*
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* Enable Snoops and DVM messages, no need for Read/Modify/Write as
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@ -150,7 +151,7 @@ void cci_enable_snoop_dvm_reqs(unsigned int master_id)
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dsbish();
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/* Wait for the dust to settle down */
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while (mmio_read_32(cci_base + STATUS_REG) & CHANGE_PENDING_BIT)
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while ((mmio_read_32(cci_base + STATUS_REG) & CHANGE_PENDING_BIT) != 0U)
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;
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}
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@ -160,7 +161,7 @@ void cci_disable_snoop_dvm_reqs(unsigned int master_id)
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assert(master_id <= max_master_id);
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assert((slave_if_id < cci_num_slave_ports) && (slave_if_id >= 0));
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assert(cci_base);
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assert(cci_base != 0U);
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/*
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* Disable Snoops and DVM messages, no need for Read/Modify/Write as
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@ -177,7 +178,7 @@ void cci_disable_snoop_dvm_reqs(unsigned int master_id)
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dsbish();
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/* Wait for the dust to settle down */
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while (mmio_read_32(cci_base + STATUS_REG) & CHANGE_PENDING_BIT)
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while ((mmio_read_32(cci_base + STATUS_REG) & CHANGE_PENDING_BIT) != 0U)
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;
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}
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -7,94 +7,96 @@
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#ifndef __CCI_H__
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#define __CCI_H__
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#include <utils_def.h>
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/* Slave interface offsets from PERIPHBASE */
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#define SLAVE_IFACE6_OFFSET 0x7000
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#define SLAVE_IFACE5_OFFSET 0x6000
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#define SLAVE_IFACE4_OFFSET 0x5000
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#define SLAVE_IFACE3_OFFSET 0x4000
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#define SLAVE_IFACE2_OFFSET 0x3000
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#define SLAVE_IFACE1_OFFSET 0x2000
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#define SLAVE_IFACE0_OFFSET 0x1000
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#define SLAVE_IFACE_OFFSET(index) (SLAVE_IFACE0_OFFSET + \
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(0x1000 * (index)))
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#define SLAVE_IFACE6_OFFSET UL(0x7000)
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#define SLAVE_IFACE5_OFFSET UL(0x6000)
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#define SLAVE_IFACE4_OFFSET UL(0x5000)
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#define SLAVE_IFACE3_OFFSET UL(0x4000)
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#define SLAVE_IFACE2_OFFSET UL(0x3000)
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#define SLAVE_IFACE1_OFFSET UL(0x2000)
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#define SLAVE_IFACE0_OFFSET UL(0x1000)
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#define SLAVE_IFACE_OFFSET(index) (SLAVE_IFACE0_OFFSET + \
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(UL(0x1000) * (index)))
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/* Slave interface event and count register offsets from PERIPHBASE */
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#define EVENT_SELECT7_OFFSET 0x80000
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#define EVENT_SELECT6_OFFSET 0x70000
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#define EVENT_SELECT5_OFFSET 0x60000
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#define EVENT_SELECT4_OFFSET 0x50000
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#define EVENT_SELECT3_OFFSET 0x40000
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#define EVENT_SELECT2_OFFSET 0x30000
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#define EVENT_SELECT1_OFFSET 0x20000
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#define EVENT_SELECT0_OFFSET 0x10000
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#define EVENT_OFFSET(index) (EVENT_SELECT0_OFFSET + \
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(0x10000 * (index)))
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#define EVENT_SELECT7_OFFSET UL(0x80000)
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#define EVENT_SELECT6_OFFSET UL(0x70000)
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#define EVENT_SELECT5_OFFSET UL(0x60000)
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#define EVENT_SELECT4_OFFSET UL(0x50000)
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#define EVENT_SELECT3_OFFSET UL(0x40000)
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#define EVENT_SELECT2_OFFSET UL(0x30000)
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#define EVENT_SELECT1_OFFSET UL(0x20000)
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#define EVENT_SELECT0_OFFSET UL(0x10000)
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#define EVENT_OFFSET(index) (EVENT_SELECT0_OFFSET + \
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(UL(0x10000) * (index)))
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/* Control and ID register offsets */
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#define CTRL_OVERRIDE_REG 0x0
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#define SECURE_ACCESS_REG 0x8
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#define STATUS_REG 0xc
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#define IMPRECISE_ERR_REG 0x10
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#define PERFMON_CTRL_REG 0x100
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#define IFACE_MON_CTRL_REG 0x104
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#define CTRL_OVERRIDE_REG U(0x0)
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#define SECURE_ACCESS_REG U(0x8)
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#define STATUS_REG U(0xc)
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#define IMPRECISE_ERR_REG U(0x10)
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#define PERFMON_CTRL_REG U(0x100)
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#define IFACE_MON_CTRL_REG U(0x104)
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/* Component and peripheral ID registers */
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#define PERIPHERAL_ID0 0xFE0
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#define PERIPHERAL_ID1 0xFE4
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#define PERIPHERAL_ID2 0xFE8
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#define PERIPHERAL_ID3 0xFEC
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#define PERIPHERAL_ID4 0xFD0
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#define PERIPHERAL_ID5 0xFD4
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#define PERIPHERAL_ID6 0xFD8
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#define PERIPHERAL_ID7 0xFDC
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#define PERIPHERAL_ID0 U(0xFE0)
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#define PERIPHERAL_ID1 U(0xFE4)
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#define PERIPHERAL_ID2 U(0xFE8)
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#define PERIPHERAL_ID3 U(0xFEC)
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#define PERIPHERAL_ID4 U(0xFD0)
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#define PERIPHERAL_ID5 U(0xFD4)
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#define PERIPHERAL_ID6 U(0xFD8)
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#define PERIPHERAL_ID7 U(0xFDC)
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#define COMPONENT_ID0 0xFF0
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#define COMPONENT_ID1 0xFF4
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#define COMPONENT_ID2 0xFF8
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#define COMPONENT_ID3 0xFFC
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#define COMPONENT_ID4 0x1000
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#define COMPONENT_ID5 0x1004
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#define COMPONENT_ID6 0x1008
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#define COMPONENT_ID7 0x100C
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#define COMPONENT_ID0 U(0xFF0)
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#define COMPONENT_ID1 U(0xFF4)
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#define COMPONENT_ID2 U(0xFF8)
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#define COMPONENT_ID3 U(0xFFC)
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#define COMPONENT_ID4 U(0x1000)
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#define COMPONENT_ID5 U(0x1004)
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#define COMPONENT_ID6 U(0x1008)
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#define COMPONENT_ID7 U(0x100C)
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/* Slave interface register offsets */
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#define SNOOP_CTRL_REG 0x0
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#define SH_OVERRIDE_REG 0x4
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#define READ_CHNL_QOS_VAL_OVERRIDE_REG 0x100
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#define WRITE_CHNL_QOS_VAL_OVERRIDE_REG 0x104
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#define MAX_OT_REG 0x110
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#define SNOOP_CTRL_REG U(0x0)
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#define SH_OVERRIDE_REG U(0x4)
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#define READ_CHNL_QOS_VAL_OVERRIDE_REG U(0x100)
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#define WRITE_CHNL_QOS_VAL_OVERRIDE_REG U(0x104)
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#define MAX_OT_REG U(0x110)
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/* Snoop Control register bit definitions */
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#define DVM_EN_BIT (1 << 1)
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#define SNOOP_EN_BIT (1 << 0)
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#define SUPPORT_SNOOPS (1 << 30)
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#define SUPPORT_DVM (1 << 31)
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#define DVM_EN_BIT BIT_32(1)
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#define SNOOP_EN_BIT BIT_32(0)
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#define SUPPORT_SNOOPS BIT_32(30)
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#define SUPPORT_DVM BIT_32(31)
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/* Status register bit definitions */
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#define CHANGE_PENDING_BIT (1 << 0)
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#define CHANGE_PENDING_BIT BIT_32(0)
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/* Event and count register offsets */
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#define EVENT_SELECT_REG 0x0
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#define EVENT_COUNT_REG 0x4
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#define COUNT_CNTRL_REG 0x8
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#define COUNT_OVERFLOW_REG 0xC
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#define EVENT_SELECT_REG U(0x0)
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#define EVENT_COUNT_REG U(0x4)
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#define COUNT_CNTRL_REG U(0x8)
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#define COUNT_OVERFLOW_REG U(0xC)
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/* Slave interface monitor registers */
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#define INT_MON_REG_SI0 0x90000
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#define INT_MON_REG_SI1 0x90004
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#define INT_MON_REG_SI2 0x90008
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#define INT_MON_REG_SI3 0x9000C
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#define INT_MON_REG_SI4 0x90010
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#define INT_MON_REG_SI5 0x90014
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#define INT_MON_REG_SI6 0x90018
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#define INT_MON_REG_SI0 U(0x90000)
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#define INT_MON_REG_SI1 U(0x90004)
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#define INT_MON_REG_SI2 U(0x90008)
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#define INT_MON_REG_SI3 U(0x9000C)
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#define INT_MON_REG_SI4 U(0x90010)
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#define INT_MON_REG_SI5 U(0x90014)
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#define INT_MON_REG_SI6 U(0x90018)
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/* Master interface monitor registers */
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#define INT_MON_REG_MI0 0x90100
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#define INT_MON_REG_MI1 0x90104
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#define INT_MON_REG_MI2 0x90108
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#define INT_MON_REG_MI3 0x9010c
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#define INT_MON_REG_MI4 0x90110
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#define INT_MON_REG_MI5 0x90114
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#define INT_MON_REG_MI0 U(0x90100)
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#define INT_MON_REG_MI1 U(0x90104)
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#define INT_MON_REG_MI2 U(0x90108)
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#define INT_MON_REG_MI3 U(0x9010c)
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#define INT_MON_REG_MI4 U(0x90110)
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#define INT_MON_REG_MI5 U(0x90114)
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#define SLAVE_IF_UNUSED -1
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