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https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-17 01:54:22 +00:00
refactor(st-gpio): code improvements
No functional, change, but some improvements:
- Declare set_gpio() as static (only called locally)
- Handle the type ('open-drain') property independently from the
mode one.
- Replace mmio_clrbits_32() + mmio_setbits_32() with
mmio_clrsetbits_32().
- Add a missing log
- Add missing U() in macro definitions
Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Change-Id: I1a79609609ac8e8001127ebefdb81def573f76fa
This commit is contained in:
Fabien Dessenne
Yann Gautier
parent
6cacfe2959
commit
417196faef
2 changed files with 56 additions and 52 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2016-2021, STMicroelectronics - All Rights Reserved
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* Copyright (c) 2016-2022, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -8,10 +8,6 @@
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#include <errno.h>
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#include <stdbool.h>
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#include <libfdt.h>
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#include <platform_def.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <drivers/clk.h>
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@ -19,6 +15,9 @@
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#include <drivers/st/stm32mp_clkfunc.h>
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#include <lib/mmio.h>
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#include <lib/utils_def.h>
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#include <libfdt.h>
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#include <platform_def.h>
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#define DT_GPIO_BANK_SHIFT 12
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#define DT_GPIO_BANK_MASK GENMASK(16, 12)
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@ -26,6 +25,10 @@
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#define DT_GPIO_PIN_MASK GENMASK(11, 8)
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#define DT_GPIO_MODE_MASK GENMASK(7, 0)
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static void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t type,
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uint32_t speed, uint32_t pull, uint32_t alternate,
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uint8_t status);
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/*******************************************************************************
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* This function gets GPIO bank node in DT.
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* Returns node offset if status is okay in DT, else return 0
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@ -100,6 +103,7 @@ static int dt_set_gpio_config(void *fdt, int node, uint8_t status)
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uint32_t pin;
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uint32_t mode;
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uint32_t alternate = GPIO_ALTERNATE_(0);
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uint32_t type;
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int bank_node;
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int clk;
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@ -129,7 +133,9 @@ static int dt_set_gpio_config(void *fdt, int node, uint8_t status)
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}
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if (fdt_getprop(fdt, node, "drive-open-drain", NULL) != NULL) {
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mode |= GPIO_OPEN_DRAIN;
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type = GPIO_TYPE_OPEN_DRAIN;
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} else {
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type = GPIO_TYPE_PUSH_PULL;
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}
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bank_node = ckeck_gpio_bank(fdt, bank, pinctrl_node);
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@ -146,7 +152,7 @@ static int dt_set_gpio_config(void *fdt, int node, uint8_t status)
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/* Platform knows the clock: assert it is okay */
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assert((unsigned long)clk == stm32_get_gpio_bank_clock(bank));
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set_gpio(bank, pin, mode, speed, pull, alternate, status);
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set_gpio(bank, pin, mode, type, speed, pull, alternate, status);
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}
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return 0;
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@ -160,7 +166,7 @@ static int dt_set_gpio_config(void *fdt, int node, uint8_t status)
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int dt_set_pinctrl_config(int node)
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{
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const fdt32_t *cuint;
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int lenp = 0;
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int lenp;
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uint32_t i;
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uint8_t status;
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void *fdt;
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@ -201,8 +207,9 @@ int dt_set_pinctrl_config(int node)
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return 0;
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}
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void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed,
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uint32_t pull, uint32_t alternate, uint8_t status)
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static void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t type,
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uint32_t speed, uint32_t pull, uint32_t alternate,
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uint8_t status)
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{
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uintptr_t base = stm32_get_gpio_bank_base(bank);
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unsigned long clock = stm32_get_gpio_bank_clock(bank);
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@ -211,41 +218,38 @@ void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed,
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clk_enable(clock);
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mmio_clrbits_32(base + GPIO_MODE_OFFSET,
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((uint32_t)GPIO_MODE_MASK << (pin << 1)));
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mmio_setbits_32(base + GPIO_MODE_OFFSET,
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(mode & ~GPIO_OPEN_DRAIN) << (pin << 1));
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mmio_clrsetbits_32(base + GPIO_MODE_OFFSET,
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(uint32_t)GPIO_MODE_MASK << (pin << 1),
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mode << (pin << 1));
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if ((mode & GPIO_OPEN_DRAIN) != 0U) {
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mmio_setbits_32(base + GPIO_TYPE_OFFSET, BIT(pin));
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} else {
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mmio_clrbits_32(base + GPIO_TYPE_OFFSET, BIT(pin));
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}
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mmio_clrsetbits_32(base + GPIO_TYPE_OFFSET,
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(uint32_t)GPIO_TYPE_MASK << pin,
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type << pin);
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mmio_clrbits_32(base + GPIO_SPEED_OFFSET,
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((uint32_t)GPIO_SPEED_MASK << (pin << 1)));
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mmio_setbits_32(base + GPIO_SPEED_OFFSET, speed << (pin << 1));
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mmio_clrsetbits_32(base + GPIO_SPEED_OFFSET,
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(uint32_t)GPIO_SPEED_MASK << (pin << 1),
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speed << (pin << 1));
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mmio_clrbits_32(base + GPIO_PUPD_OFFSET,
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((uint32_t)GPIO_PULL_MASK << (pin << 1)));
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mmio_setbits_32(base + GPIO_PUPD_OFFSET, pull << (pin << 1));
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mmio_clrsetbits_32(base + GPIO_PUPD_OFFSET,
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(uint32_t)GPIO_PULL_MASK << (pin << 1),
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pull << (pin << 1));
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if (pin < GPIO_ALT_LOWER_LIMIT) {
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mmio_clrbits_32(base + GPIO_AFRL_OFFSET,
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((uint32_t)GPIO_ALTERNATE_MASK << (pin << 2)));
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mmio_setbits_32(base + GPIO_AFRL_OFFSET,
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alternate << (pin << 2));
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mmio_clrsetbits_32(base + GPIO_AFRL_OFFSET,
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(uint32_t)GPIO_ALTERNATE_MASK << (pin << 2),
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alternate << (pin << 2));
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} else {
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mmio_clrbits_32(base + GPIO_AFRH_OFFSET,
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((uint32_t)GPIO_ALTERNATE_MASK <<
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((pin - GPIO_ALT_LOWER_LIMIT) << 2)));
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mmio_setbits_32(base + GPIO_AFRH_OFFSET,
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alternate << ((pin - GPIO_ALT_LOWER_LIMIT) <<
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2));
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size_t shift = (pin - GPIO_ALT_LOWER_LIMIT) << 2;
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mmio_clrsetbits_32(base + GPIO_AFRH_OFFSET,
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(uint32_t)GPIO_ALTERNATE_MASK << shift,
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alternate << shift);
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}
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VERBOSE("GPIO %u mode set to 0x%x\n", bank,
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mmio_read_32(base + GPIO_MODE_OFFSET));
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VERBOSE("GPIO %u type set to 0x%x\n", bank,
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mmio_read_32(base + GPIO_TYPE_OFFSET));
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VERBOSE("GPIO %u speed set to 0x%x\n", bank,
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mmio_read_32(base + GPIO_SPEED_OFFSET));
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VERBOSE("GPIO %u mode pull to 0x%x\n", bank,
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@ -287,7 +291,7 @@ void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure)
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void set_gpio_reset_cfg(uint32_t bank, uint32_t pin)
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{
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set_gpio(bank, pin, GPIO_MODE_ANALOG, GPIO_SPEED_LOW,
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GPIO_NO_PULL, GPIO_ALTERNATE_(0), DT_DISABLED);
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set_gpio(bank, pin, GPIO_MODE_ANALOG, GPIO_TYPE_PUSH_PULL,
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GPIO_SPEED_LOW, GPIO_NO_PULL, GPIO_ALTERNATE_(0), DT_DISABLED);
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set_gpio_secure_cfg(bank, pin, stm32_gpio_is_secure_at_reset(bank));
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}
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2021, STMicroelectronics - All Rights Reserved
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* Copyright (c) 2015-2022, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -26,31 +26,31 @@
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#define GPIO_ALTERNATE_(_x) U(_x)
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#define GPIO_ALTERNATE_MASK U(0x0F)
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#define GPIO_MODE_INPUT 0x00
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#define GPIO_MODE_OUTPUT 0x01
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#define GPIO_MODE_ALTERNATE 0x02
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#define GPIO_MODE_ANALOG 0x03
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#define GPIO_MODE_INPUT U(0x00)
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#define GPIO_MODE_OUTPUT U(0x01)
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#define GPIO_MODE_ALTERNATE U(0x02)
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#define GPIO_MODE_ANALOG U(0x03)
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#define GPIO_MODE_MASK U(0x03)
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#define GPIO_OPEN_DRAIN U(0x10)
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#define GPIO_TYPE_PUSH_PULL U(0x00)
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#define GPIO_TYPE_OPEN_DRAIN U(0x01)
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#define GPIO_TYPE_MASK U(0x01)
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#define GPIO_SPEED_LOW 0x00
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#define GPIO_SPEED_MEDIUM 0x01
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#define GPIO_SPEED_HIGH 0x02
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#define GPIO_SPEED_VERY_HIGH 0x03
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#define GPIO_SPEED_LOW U(0x00)
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#define GPIO_SPEED_MEDIUM U(0x01)
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#define GPIO_SPEED_HIGH U(0x02)
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#define GPIO_SPEED_VERY_HIGH U(0x03)
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#define GPIO_SPEED_MASK U(0x03)
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#define GPIO_NO_PULL 0x00
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#define GPIO_PULL_UP 0x01
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#define GPIO_PULL_DOWN 0x02
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#define GPIO_NO_PULL U(0x00)
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#define GPIO_PULL_UP U(0x01)
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#define GPIO_PULL_DOWN U(0x02)
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#define GPIO_PULL_MASK U(0x03)
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#ifndef __ASSEMBLER__
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#include <stdint.h>
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int dt_set_pinctrl_config(int node);
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void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed,
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uint32_t pull, uint32_t alternate, uint8_t status);
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void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure);
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void set_gpio_reset_cfg(uint32_t bank, uint32_t pin);
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#endif /*__ASSEMBLER__*/
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