mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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drivers/emmc: remove emmc framework
Replace emmc framework by mmc framework. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
This commit is contained in:
Haojian Zhuang
parent
eba1b6b3c7
commit
41583c5781
2 changed files with 0 additions and 528 deletions
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@ -1,363 +0,0 @@
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/*
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* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Defines a simple and generic interface to access eMMC device.
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <debug.h>
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#include <emmc.h>
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#include <errno.h>
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#include <string.h>
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#include <utils.h>
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static const emmc_ops_t *ops;
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static unsigned int emmc_ocr_value;
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static emmc_csd_t emmc_csd;
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static unsigned int emmc_flags;
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static int is_cmd23_enabled(void)
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{
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return (!!(emmc_flags & EMMC_FLAG_CMD23));
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}
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static int emmc_device_state(void)
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{
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emmc_cmd_t cmd;
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int ret;
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do {
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zeromem(&cmd, sizeof(emmc_cmd_t));
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cmd.cmd_idx = EMMC_CMD13;
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cmd.cmd_arg = EMMC_FIX_RCA << RCA_SHIFT_OFFSET;
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cmd.resp_type = EMMC_RESPONSE_R1;
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ret = ops->send_cmd(&cmd);
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assert(ret == 0);
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assert((cmd.resp_data[0] & STATUS_SWITCH_ERROR) == 0);
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/* Ignore improbable errors in release builds */
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(void)ret;
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} while ((cmd.resp_data[0] & STATUS_READY_FOR_DATA) == 0);
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return EMMC_GET_STATE(cmd.resp_data[0]);
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}
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static void emmc_set_ext_csd(unsigned int ext_cmd, unsigned int value)
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{
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emmc_cmd_t cmd;
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int ret, state;
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zeromem(&cmd, sizeof(emmc_cmd_t));
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cmd.cmd_idx = EMMC_CMD6;
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cmd.cmd_arg = EXTCSD_WRITE_BYTES | EXTCSD_CMD(ext_cmd) |
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EXTCSD_VALUE(value) | 1;
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ret = ops->send_cmd(&cmd);
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assert(ret == 0);
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/* wait to exit PRG state */
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do {
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state = emmc_device_state();
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} while (state == EMMC_STATE_PRG);
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/* Ignore improbable errors in release builds */
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(void)ret;
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}
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static void emmc_set_ios(int clk, int bus_width)
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{
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int ret;
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/* set IO speed & IO bus width */
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if (emmc_csd.spec_vers == 4)
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emmc_set_ext_csd(CMD_EXTCSD_BUS_WIDTH, bus_width);
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ret = ops->set_ios(clk, bus_width);
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assert(ret == 0);
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/* Ignore improbable errors in release builds */
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(void)ret;
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}
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static int emmc_enumerate(int clk, int bus_width)
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{
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emmc_cmd_t cmd;
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int ret, state;
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ops->init();
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/* CMD0: reset to IDLE */
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zeromem(&cmd, sizeof(emmc_cmd_t));
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cmd.cmd_idx = EMMC_CMD0;
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ret = ops->send_cmd(&cmd);
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assert(ret == 0);
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while (1) {
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/* CMD1: get OCR register */
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zeromem(&cmd, sizeof(emmc_cmd_t));
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cmd.cmd_idx = EMMC_CMD1;
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cmd.cmd_arg = OCR_SECTOR_MODE | OCR_VDD_MIN_2V7 |
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OCR_VDD_MIN_1V7;
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cmd.resp_type = EMMC_RESPONSE_R3;
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ret = ops->send_cmd(&cmd);
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assert(ret == 0);
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emmc_ocr_value = cmd.resp_data[0];
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if (emmc_ocr_value & OCR_POWERUP)
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break;
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}
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/* CMD2: Card Identification */
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zeromem(&cmd, sizeof(emmc_cmd_t));
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cmd.cmd_idx = EMMC_CMD2;
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cmd.resp_type = EMMC_RESPONSE_R2;
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ret = ops->send_cmd(&cmd);
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assert(ret == 0);
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/* CMD3: Set Relative Address */
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zeromem(&cmd, sizeof(emmc_cmd_t));
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cmd.cmd_idx = EMMC_CMD3;
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cmd.cmd_arg = EMMC_FIX_RCA << RCA_SHIFT_OFFSET;
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cmd.resp_type = EMMC_RESPONSE_R1;
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ret = ops->send_cmd(&cmd);
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assert(ret == 0);
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/* CMD9: CSD Register */
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zeromem(&cmd, sizeof(emmc_cmd_t));
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cmd.cmd_idx = EMMC_CMD9;
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cmd.cmd_arg = EMMC_FIX_RCA << RCA_SHIFT_OFFSET;
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cmd.resp_type = EMMC_RESPONSE_R2;
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ret = ops->send_cmd(&cmd);
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assert(ret == 0);
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memcpy(&emmc_csd, &cmd.resp_data, sizeof(cmd.resp_data));
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/* CMD7: Select Card */
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zeromem(&cmd, sizeof(emmc_cmd_t));
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cmd.cmd_idx = EMMC_CMD7;
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cmd.cmd_arg = EMMC_FIX_RCA << RCA_SHIFT_OFFSET;
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cmd.resp_type = EMMC_RESPONSE_R1;
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ret = ops->send_cmd(&cmd);
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assert(ret == 0);
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/* wait to TRAN state */
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do {
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state = emmc_device_state();
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} while (state != EMMC_STATE_TRAN);
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emmc_set_ios(clk, bus_width);
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return ret;
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}
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size_t emmc_read_blocks(int lba, uintptr_t buf, size_t size)
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{
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emmc_cmd_t cmd;
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int ret;
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assert((ops != 0) &&
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(ops->read != 0) &&
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((buf & EMMC_BLOCK_MASK) == 0) &&
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((size & EMMC_BLOCK_MASK) == 0));
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inv_dcache_range(buf, size);
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ret = ops->prepare(lba, buf, size);
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assert(ret == 0);
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if (is_cmd23_enabled()) {
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zeromem(&cmd, sizeof(emmc_cmd_t));
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/* set block count */
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cmd.cmd_idx = EMMC_CMD23;
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cmd.cmd_arg = size / EMMC_BLOCK_SIZE;
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cmd.resp_type = EMMC_RESPONSE_R1;
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ret = ops->send_cmd(&cmd);
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assert(ret == 0);
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zeromem(&cmd, sizeof(emmc_cmd_t));
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cmd.cmd_idx = EMMC_CMD18;
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} else {
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if (size > EMMC_BLOCK_SIZE)
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cmd.cmd_idx = EMMC_CMD18;
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else
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cmd.cmd_idx = EMMC_CMD17;
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}
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if ((emmc_ocr_value & OCR_ACCESS_MODE_MASK) == OCR_BYTE_MODE)
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cmd.cmd_arg = lba * EMMC_BLOCK_SIZE;
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else
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cmd.cmd_arg = lba;
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cmd.resp_type = EMMC_RESPONSE_R1;
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ret = ops->send_cmd(&cmd);
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assert(ret == 0);
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ret = ops->read(lba, buf, size);
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assert(ret == 0);
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/* wait buffer empty */
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emmc_device_state();
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if (is_cmd23_enabled() == 0) {
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if (size > EMMC_BLOCK_SIZE) {
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zeromem(&cmd, sizeof(emmc_cmd_t));
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cmd.cmd_idx = EMMC_CMD12;
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ret = ops->send_cmd(&cmd);
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assert(ret == 0);
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}
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}
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/* Ignore improbable errors in release builds */
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(void)ret;
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return size;
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}
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size_t emmc_write_blocks(int lba, const uintptr_t buf, size_t size)
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{
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emmc_cmd_t cmd;
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int ret;
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assert((ops != 0) &&
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(ops->write != 0) &&
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((buf & EMMC_BLOCK_MASK) == 0) &&
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((size & EMMC_BLOCK_MASK) == 0));
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clean_dcache_range(buf, size);
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ret = ops->prepare(lba, buf, size);
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assert(ret == 0);
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if (is_cmd23_enabled()) {
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/* set block count */
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zeromem(&cmd, sizeof(emmc_cmd_t));
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cmd.cmd_idx = EMMC_CMD23;
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cmd.cmd_arg = size / EMMC_BLOCK_SIZE;
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cmd.resp_type = EMMC_RESPONSE_R1;
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ret = ops->send_cmd(&cmd);
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assert(ret == 0);
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zeromem(&cmd, sizeof(emmc_cmd_t));
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cmd.cmd_idx = EMMC_CMD25;
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} else {
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zeromem(&cmd, sizeof(emmc_cmd_t));
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if (size > EMMC_BLOCK_SIZE)
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cmd.cmd_idx = EMMC_CMD25;
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else
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cmd.cmd_idx = EMMC_CMD24;
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}
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if ((emmc_ocr_value & OCR_ACCESS_MODE_MASK) == OCR_BYTE_MODE)
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cmd.cmd_arg = lba * EMMC_BLOCK_SIZE;
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else
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cmd.cmd_arg = lba;
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cmd.resp_type = EMMC_RESPONSE_R1;
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ret = ops->send_cmd(&cmd);
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assert(ret == 0);
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ret = ops->write(lba, buf, size);
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assert(ret == 0);
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/* wait buffer empty */
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emmc_device_state();
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if (is_cmd23_enabled() == 0) {
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if (size > EMMC_BLOCK_SIZE) {
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zeromem(&cmd, sizeof(emmc_cmd_t));
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cmd.cmd_idx = EMMC_CMD12;
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ret = ops->send_cmd(&cmd);
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assert(ret == 0);
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}
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}
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/* Ignore improbable errors in release builds */
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(void)ret;
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return size;
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}
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size_t emmc_erase_blocks(int lba, size_t size)
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{
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emmc_cmd_t cmd;
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int ret, state;
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assert(ops != 0);
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assert((size != 0) && ((size % EMMC_BLOCK_SIZE) == 0));
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zeromem(&cmd, sizeof(emmc_cmd_t));
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cmd.cmd_idx = EMMC_CMD35;
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cmd.cmd_arg = lba;
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cmd.resp_type = EMMC_RESPONSE_R1;
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ret = ops->send_cmd(&cmd);
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assert(ret == 0);
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zeromem(&cmd, sizeof(emmc_cmd_t));
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cmd.cmd_idx = EMMC_CMD36;
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cmd.cmd_arg = lba + (size / EMMC_BLOCK_SIZE) - 1;
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cmd.resp_type = EMMC_RESPONSE_R1;
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ret = ops->send_cmd(&cmd);
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assert(ret == 0);
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zeromem(&cmd, sizeof(emmc_cmd_t));
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cmd.cmd_idx = EMMC_CMD38;
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cmd.resp_type = EMMC_RESPONSE_R1B;
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ret = ops->send_cmd(&cmd);
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assert(ret == 0);
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/* wait to TRAN state */
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do {
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state = emmc_device_state();
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} while (state != EMMC_STATE_TRAN);
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/* Ignore improbable errors in release builds */
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(void)ret;
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return size;
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}
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static inline void emmc_rpmb_enable(void)
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{
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emmc_set_ext_csd(CMD_EXTCSD_PARTITION_CONFIG,
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PART_CFG_BOOT_PARTITION1_ENABLE |
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PART_CFG_PARTITION1_ACCESS);
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}
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static inline void emmc_rpmb_disable(void)
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{
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emmc_set_ext_csd(CMD_EXTCSD_PARTITION_CONFIG,
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PART_CFG_BOOT_PARTITION1_ENABLE);
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}
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size_t emmc_rpmb_read_blocks(int lba, uintptr_t buf, size_t size)
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{
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size_t size_read;
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emmc_rpmb_enable();
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size_read = emmc_read_blocks(lba, buf, size);
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emmc_rpmb_disable();
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return size_read;
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}
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size_t emmc_rpmb_write_blocks(int lba, const uintptr_t buf, size_t size)
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{
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size_t size_written;
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emmc_rpmb_enable();
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size_written = emmc_write_blocks(lba, buf, size);
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emmc_rpmb_disable();
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return size_written;
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}
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size_t emmc_rpmb_erase_blocks(int lba, size_t size)
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{
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size_t size_erased;
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emmc_rpmb_enable();
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size_erased = emmc_erase_blocks(lba, size);
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emmc_rpmb_disable();
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return size_erased;
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}
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void emmc_init(const emmc_ops_t *ops_ptr, int clk, int width,
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unsigned int flags)
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{
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assert((ops_ptr != 0) &&
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(ops_ptr->init != 0) &&
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(ops_ptr->send_cmd != 0) &&
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(ops_ptr->set_ios != 0) &&
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(ops_ptr->prepare != 0) &&
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(ops_ptr->read != 0) &&
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(ops_ptr->write != 0) &&
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(clk != 0) &&
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((width == EMMC_BUS_WIDTH_1) ||
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(width == EMMC_BUS_WIDTH_4) ||
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(width == EMMC_BUS_WIDTH_8) ||
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(width == EMMC_BUS_WIDTH_DDR_4) ||
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(width == EMMC_BUS_WIDTH_DDR_8)));
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ops = ops_ptr;
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emmc_flags = flags;
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emmc_enumerate(clk, width);
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}
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@ -1,165 +0,0 @@
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/*
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* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __EMMC_H__
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#define __EMMC_H__
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#include <stdint.h>
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#define EMMC_BLOCK_SIZE 512
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#define EMMC_BLOCK_MASK (EMMC_BLOCK_SIZE - 1)
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#define EMMC_BOOT_CLK_RATE (400 * 1000)
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#define EMMC_CMD0 0
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#define EMMC_CMD1 1
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#define EMMC_CMD2 2
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#define EMMC_CMD3 3
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#define EMMC_CMD6 6
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#define EMMC_CMD7 7
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#define EMMC_CMD8 8
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#define EMMC_CMD9 9
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#define EMMC_CMD12 12
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#define EMMC_CMD13 13
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#define EMMC_CMD17 17
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#define EMMC_CMD18 18
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#define EMMC_CMD21 21
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#define EMMC_CMD23 23
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#define EMMC_CMD24 24
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#define EMMC_CMD25 25
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#define EMMC_CMD35 35
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#define EMMC_CMD36 36
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#define EMMC_CMD38 38
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#define OCR_POWERUP (1 << 31)
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#define OCR_BYTE_MODE (0 << 29)
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#define OCR_SECTOR_MODE (2 << 29)
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#define OCR_ACCESS_MODE_MASK (3 << 29)
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#define OCR_VDD_MIN_2V7 (0x1ff << 15)
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#define OCR_VDD_MIN_2V0 (0x7f << 8)
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#define OCR_VDD_MIN_1V7 (1 << 7)
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#define EMMC_RESPONSE_R1 1
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#define EMMC_RESPONSE_R1B 1
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#define EMMC_RESPONSE_R2 4
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#define EMMC_RESPONSE_R3 1
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#define EMMC_RESPONSE_R4 1
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#define EMMC_RESPONSE_R5 1
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#define EMMC_FIX_RCA 6 /* > 1 */
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#define RCA_SHIFT_OFFSET 16
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#define CMD_EXTCSD_PARTITION_CONFIG 179
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#define CMD_EXTCSD_BUS_WIDTH 183
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#define CMD_EXTCSD_HS_TIMING 185
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#define PART_CFG_BOOT_PARTITION1_ENABLE (1 << 3)
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#define PART_CFG_PARTITION1_ACCESS (1 << 0)
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/* values in EXT CSD register */
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#define EMMC_BUS_WIDTH_1 0
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#define EMMC_BUS_WIDTH_4 1
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#define EMMC_BUS_WIDTH_8 2
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#define EMMC_BUS_WIDTH_DDR_4 5
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#define EMMC_BUS_WIDTH_DDR_8 6
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#define EMMC_BOOT_MODE_BACKWARD (0 << 3)
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#define EMMC_BOOT_MODE_HS_TIMING (1 << 3)
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#define EMMC_BOOT_MODE_DDR (2 << 3)
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#define EXTCSD_SET_CMD (0 << 24)
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#define EXTCSD_SET_BITS (1 << 24)
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#define EXTCSD_CLR_BITS (2 << 24)
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#define EXTCSD_WRITE_BYTES (3 << 24)
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#define EXTCSD_CMD(x) (((x) & 0xff) << 16)
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#define EXTCSD_VALUE(x) (((x) & 0xff) << 8)
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#define STATUS_CURRENT_STATE(x) (((x) & 0xf) << 9)
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#define STATUS_READY_FOR_DATA (1 << 8)
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#define STATUS_SWITCH_ERROR (1 << 7)
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#define EMMC_GET_STATE(x) (((x) >> 9) & 0xf)
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#define EMMC_STATE_IDLE 0
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#define EMMC_STATE_READY 1
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#define EMMC_STATE_IDENT 2
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#define EMMC_STATE_STBY 3
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#define EMMC_STATE_TRAN 4
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#define EMMC_STATE_DATA 5
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#define EMMC_STATE_RCV 6
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#define EMMC_STATE_PRG 7
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#define EMMC_STATE_DIS 8
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#define EMMC_STATE_BTST 9
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#define EMMC_STATE_SLP 10
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|
||||
#define EMMC_FLAG_CMD23 (1 << 0)
|
||||
|
||||
typedef struct emmc_cmd {
|
||||
unsigned int cmd_idx;
|
||||
unsigned int cmd_arg;
|
||||
unsigned int resp_type;
|
||||
unsigned int resp_data[4];
|
||||
} emmc_cmd_t;
|
||||
|
||||
typedef struct emmc_ops {
|
||||
void (*init)(void);
|
||||
int (*send_cmd)(emmc_cmd_t *cmd);
|
||||
int (*set_ios)(int clk, int width);
|
||||
int (*prepare)(int lba, uintptr_t buf, size_t size);
|
||||
int (*read)(int lba, uintptr_t buf, size_t size);
|
||||
int (*write)(int lba, const uintptr_t buf, size_t size);
|
||||
} emmc_ops_t;
|
||||
|
||||
typedef struct emmc_csd {
|
||||
unsigned int not_used: 1;
|
||||
unsigned int crc: 7;
|
||||
unsigned int ecc: 2;
|
||||
unsigned int file_format: 2;
|
||||
unsigned int tmp_write_protect: 1;
|
||||
unsigned int perm_write_protect: 1;
|
||||
unsigned int copy: 1;
|
||||
unsigned int file_format_grp: 1;
|
||||
|
||||
unsigned int reserved_1: 5;
|
||||
unsigned int write_bl_partial: 1;
|
||||
unsigned int write_bl_len: 4;
|
||||
unsigned int r2w_factor: 3;
|
||||
unsigned int default_ecc: 2;
|
||||
unsigned int wp_grp_enable: 1;
|
||||
|
||||
unsigned int wp_grp_size: 5;
|
||||
unsigned int erase_grp_mult: 5;
|
||||
unsigned int erase_grp_size: 5;
|
||||
unsigned int c_size_mult: 3;
|
||||
unsigned int vdd_w_curr_max: 3;
|
||||
unsigned int vdd_w_curr_min: 3;
|
||||
unsigned int vdd_r_curr_max: 3;
|
||||
unsigned int vdd_r_curr_min: 3;
|
||||
unsigned int c_size_low: 2;
|
||||
|
||||
unsigned int c_size_high: 10;
|
||||
unsigned int reserved_2: 2;
|
||||
unsigned int dsr_imp: 1;
|
||||
unsigned int read_blk_misalign: 1;
|
||||
unsigned int write_blk_misalign: 1;
|
||||
unsigned int read_bl_partial: 1;
|
||||
unsigned int read_bl_len: 4;
|
||||
unsigned int ccc: 12;
|
||||
|
||||
unsigned int tran_speed: 8;
|
||||
unsigned int nsac: 8;
|
||||
unsigned int taac: 8;
|
||||
unsigned int reserved_3: 2;
|
||||
unsigned int spec_vers: 4;
|
||||
unsigned int csd_structure: 2;
|
||||
} emmc_csd_t;
|
||||
|
||||
size_t emmc_read_blocks(int lba, uintptr_t buf, size_t size);
|
||||
size_t emmc_write_blocks(int lba, const uintptr_t buf, size_t size);
|
||||
size_t emmc_erase_blocks(int lba, size_t size);
|
||||
size_t emmc_rpmb_read_blocks(int lba, uintptr_t buf, size_t size);
|
||||
size_t emmc_rpmb_write_blocks(int lba, const uintptr_t buf, size_t size);
|
||||
size_t emmc_rpmb_erase_blocks(int lba, size_t size);
|
||||
void emmc_init(const emmc_ops_t *ops, int clk, int bus_width,
|
||||
unsigned int flags);
|
||||
|
||||
#endif /* __EMMC_H__ */
|
||||
Loading…
Add table
Reference in a new issue