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drivers: st: update drivers code
Reword some traces. Use uintptr_t where required. Reduce scope of variables. Improve io_stm32image algo. Complete some IP registers definitions. Add failure on supported DDR (stm32mp1_ddr_init()). Fix cache flush on cache disable (stm32mp1_ddr_setup). Change-Id: Ie02fa71e02b9d69abc807fd5b7df233e5be6668c Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
This commit is contained in:
Yann Gautier
parent
077f682853
commit
4156d4daa8
9 changed files with 348 additions and 183 deletions
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@ -4,6 +4,7 @@
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* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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*/
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#include <errno.h>
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#include <stddef.h>
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#include <platform_def.h>
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@ -233,40 +234,67 @@ struct ddr_reg_info {
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static const struct ddr_reg_info ddr_registers[REG_TYPE_NB] = {
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[REG_REG] = {
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"static", ddr_reg, ARRAY_SIZE(ddr_reg), DDR_BASE
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.name = "static",
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.desc = ddr_reg,
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.size = ARRAY_SIZE(ddr_reg),
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.base = DDR_BASE
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},
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[REG_TIMING] = {
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"timing", ddr_timing, ARRAY_SIZE(ddr_timing), DDR_BASE
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.name = "timing",
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.desc = ddr_timing,
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.size = ARRAY_SIZE(ddr_timing),
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.base = DDR_BASE
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},
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[REG_PERF] = {
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"perf", ddr_perf, ARRAY_SIZE(ddr_perf), DDR_BASE
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.name = "perf",
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.desc = ddr_perf,
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.size = ARRAY_SIZE(ddr_perf),
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.base = DDR_BASE
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},
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[REG_MAP] = {
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"map", ddr_map, ARRAY_SIZE(ddr_map), DDR_BASE
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.name = "map",
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.desc = ddr_map,
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.size = ARRAY_SIZE(ddr_map),
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.base = DDR_BASE
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},
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[REGPHY_REG] = {
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"static", ddrphy_reg, ARRAY_SIZE(ddrphy_reg), DDRPHY_BASE
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.name = "static",
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.desc = ddrphy_reg,
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.size = ARRAY_SIZE(ddrphy_reg),
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.base = DDRPHY_BASE
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},
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[REGPHY_TIMING] = {
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"timing", ddrphy_timing, ARRAY_SIZE(ddrphy_timing), DDRPHY_BASE
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.name = "timing",
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.desc = ddrphy_timing,
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.size = ARRAY_SIZE(ddrphy_timing),
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.base = DDRPHY_BASE
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},
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[REGPHY_CAL] = {
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"cal", ddrphy_cal, ARRAY_SIZE(ddrphy_cal), DDRPHY_BASE
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.name = "cal",
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.desc = ddrphy_cal,
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.size = ARRAY_SIZE(ddrphy_cal),
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.base = DDRPHY_BASE
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},
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[REG_DYN] = {
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"dyn", ddr_dyn, ARRAY_SIZE(ddr_dyn), DDR_BASE
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.name = "dyn",
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.desc = ddr_dyn,
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.size = ARRAY_SIZE(ddr_dyn),
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.base = DDR_BASE
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},
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[REGPHY_DYN] = {
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"dyn", ddrphy_dyn, ARRAY_SIZE(ddrphy_dyn), DDRPHY_BASE
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.name = "dyn",
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.desc = ddrphy_dyn,
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.size = ARRAY_SIZE(ddrphy_dyn),
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.base = DDRPHY_BASE
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},
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};
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static uint32_t get_base_addr(const struct ddr_info *priv, enum base_type base)
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static uintptr_t get_base_addr(const struct ddr_info *priv, enum base_type base)
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{
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if (base == DDRPHY_BASE) {
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return (uint32_t)priv->phy;
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return (uintptr_t)priv->phy;
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} else {
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return (uint32_t)priv->ctl;
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return (uintptr_t)priv->ctl;
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}
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}
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@ -275,21 +303,22 @@ static void set_reg(const struct ddr_info *priv,
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const void *param)
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{
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unsigned int i;
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unsigned int *ptr, value;
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unsigned int value;
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enum base_type base = ddr_registers[type].base;
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uint32_t base_addr = get_base_addr(priv, base);
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uintptr_t base_addr = get_base_addr(priv, base);
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const struct reg_desc *desc = ddr_registers[type].desc;
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VERBOSE("init %s\n", ddr_registers[type].name);
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for (i = 0; i < ddr_registers[type].size; i++) {
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ptr = (unsigned int *)(base_addr + desc[i].offset);
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uintptr_t ptr = base_addr + desc[i].offset;
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if (desc[i].par_offset == INVALID_OFFSET) {
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ERROR("invalid parameter offset for %s", desc[i].name);
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panic();
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} else {
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value = *((uint32_t *)((uint32_t)param +
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value = *((uint32_t *)((uintptr_t)param +
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desc[i].par_offset));
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mmio_write_32((uint32_t)ptr, value);
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mmio_write_32(ptr, value);
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}
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}
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}
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@ -305,15 +334,15 @@ static void stm32mp1_ddrphy_idone_wait(struct stm32mp1_ddrphy *phy)
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time0 = start;
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do {
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pgsr = mmio_read_32((uint32_t)&phy->pgsr);
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pgsr = mmio_read_32((uintptr_t)&phy->pgsr);
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time = get_timer(start);
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if (time != time0) {
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VERBOSE(" > [0x%x] pgsr = 0x%x &\n",
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(uint32_t)&phy->pgsr, pgsr);
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VERBOSE(" [0x%x] pir = 0x%x (time=%x)\n",
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(uint32_t)&phy->pir,
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mmio_read_32((uint32_t)&phy->pir),
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(uint32_t)time);
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VERBOSE(" > [0x%lx] pgsr = 0x%x &\n",
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(uintptr_t)&phy->pgsr, pgsr);
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VERBOSE(" [0x%lx] pir = 0x%x (time=%lx)\n",
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(uintptr_t)&phy->pir,
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mmio_read_32((uintptr_t)&phy->pir),
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time);
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}
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time0 = time;
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@ -341,18 +370,18 @@ static void stm32mp1_ddrphy_idone_wait(struct stm32mp1_ddrphy *phy)
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error++;
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}
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} while ((pgsr & DDRPHYC_PGSR_IDONE) == 0U && error == 0);
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VERBOSE("\n[0x%x] pgsr = 0x%x\n",
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(uint32_t)&phy->pgsr, pgsr);
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VERBOSE("\n[0x%lx] pgsr = 0x%x\n",
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(uintptr_t)&phy->pgsr, pgsr);
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}
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static void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, uint32_t pir)
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{
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uint32_t pir_init = pir | DDRPHYC_PIR_INIT;
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mmio_write_32((uint32_t)&phy->pir, pir_init);
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VERBOSE("[0x%x] pir = 0x%x -> 0x%x\n",
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(uint32_t)&phy->pir, pir_init,
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mmio_read_32((uint32_t)&phy->pir));
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mmio_write_32((uintptr_t)&phy->pir, pir_init);
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VERBOSE("[0x%lx] pir = 0x%x -> 0x%x\n",
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(uintptr_t)&phy->pir, pir_init,
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mmio_read_32((uintptr_t)&phy->pir));
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/* Need to wait 10 configuration clock before start polling */
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udelay(10);
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@ -364,9 +393,9 @@ static void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, uint32_t pir)
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/* Start quasi dynamic register update */
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static void stm32mp1_start_sw_done(struct stm32mp1_ddrctl *ctl)
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{
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mmio_clrbits_32((uint32_t)&ctl->swctl, DDRCTRL_SWCTL_SW_DONE);
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VERBOSE("[0x%x] swctl = 0x%x\n",
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(uint32_t)&ctl->swctl, mmio_read_32((uint32_t)&ctl->swctl));
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mmio_clrbits_32((uintptr_t)&ctl->swctl, DDRCTRL_SWCTL_SW_DONE);
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VERBOSE("[0x%lx] swctl = 0x%x\n",
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(uintptr_t)&ctl->swctl, mmio_read_32((uintptr_t)&ctl->swctl));
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}
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/* Wait quasi dynamic register update */
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@ -375,15 +404,15 @@ static void stm32mp1_wait_sw_done_ack(struct stm32mp1_ddrctl *ctl)
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unsigned long start;
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uint32_t swstat;
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mmio_setbits_32((uint32_t)&ctl->swctl, DDRCTRL_SWCTL_SW_DONE);
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VERBOSE("[0x%x] swctl = 0x%x\n",
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(uint32_t)&ctl->swctl, mmio_read_32((uint32_t)&ctl->swctl));
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mmio_setbits_32((uintptr_t)&ctl->swctl, DDRCTRL_SWCTL_SW_DONE);
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VERBOSE("[0x%lx] swctl = 0x%x\n",
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(uintptr_t)&ctl->swctl, mmio_read_32((uintptr_t)&ctl->swctl));
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start = get_timer(0);
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do {
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swstat = mmio_read_32((uint32_t)&ctl->swstat);
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VERBOSE("[0x%x] swstat = 0x%x ",
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(uint32_t)&ctl->swstat, swstat);
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swstat = mmio_read_32((uintptr_t)&ctl->swstat);
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VERBOSE("[0x%lx] swstat = 0x%x ",
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(uintptr_t)&ctl->swstat, swstat);
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VERBOSE("timer in ms 0x%x = start 0x%lx\r",
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get_timer(0), start);
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if (get_timer(start) > plat_get_syscnt_freq2()) {
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@ -391,8 +420,8 @@ static void stm32mp1_wait_sw_done_ack(struct stm32mp1_ddrctl *ctl)
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}
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} while ((swstat & DDRCTRL_SWSTAT_SW_DONE_ACK) == 0U);
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VERBOSE("[0x%x] swstat = 0x%x\n",
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(uint32_t)&ctl->swstat, swstat);
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VERBOSE("[0x%lx] swstat = 0x%x\n",
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(uintptr_t)&ctl->swstat, swstat);
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}
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/* Wait quasi dynamic register update */
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@ -406,11 +435,11 @@ static void stm32mp1_wait_operating_mode(struct ddr_info *priv, uint32_t mode)
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start = get_timer(0);
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for ( ; ; ) {
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stat = mmio_read_32((uint32_t)&priv->ctl->stat);
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stat = mmio_read_32((uintptr_t)&priv->ctl->stat);
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operating_mode = stat & DDRCTRL_STAT_OPERATING_MODE_MASK;
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selref_type = stat & DDRCTRL_STAT_SELFREF_TYPE_MASK;
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VERBOSE("[0x%x] stat = 0x%x\n",
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(uint32_t)&priv->ctl->stat, stat);
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VERBOSE("[0x%lx] stat = 0x%x\n",
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(uintptr_t)&priv->ctl->stat, stat);
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VERBOSE("timer in ms 0x%x = start 0x%lx\r",
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get_timer(0), start);
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if (get_timer(start) > plat_get_syscnt_freq2()) {
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@ -441,8 +470,8 @@ static void stm32mp1_wait_operating_mode(struct ddr_info *priv, uint32_t mode)
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}
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}
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VERBOSE("[0x%x] stat = 0x%x\n",
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(uint32_t)&priv->ctl->stat, stat);
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VERBOSE("[0x%lx] stat = 0x%x\n",
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(uintptr_t)&priv->ctl->stat, stat);
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}
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/* Mode Register Writes (MRW or MRS) */
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@ -459,7 +488,7 @@ static void stm32mp1_mode_register_write(struct ddr_info *priv, uint8_t addr,
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* No write should be performed to MRCTRL0 and MRCTRL1
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* if MRSTAT.mr_wr_busy = 1.
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*/
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while ((mmio_read_32((uint32_t)&priv->ctl->mrstat) &
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while ((mmio_read_32((uintptr_t)&priv->ctl->mrstat) &
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DDRCTRL_MRSTAT_MR_WR_BUSY) != 0U) {
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;
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}
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@ -472,14 +501,14 @@ static void stm32mp1_mode_register_write(struct ddr_info *priv, uint8_t addr,
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DDRCTRL_MRCTRL0_MR_RANK_ALL |
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(((uint32_t)addr << DDRCTRL_MRCTRL0_MR_ADDR_SHIFT) &
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DDRCTRL_MRCTRL0_MR_ADDR_MASK);
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mmio_write_32((uint32_t)&priv->ctl->mrctrl0, mrctrl0);
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VERBOSE("[0x%x] mrctrl0 = 0x%x (0x%x)\n",
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(uint32_t)&priv->ctl->mrctrl0,
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mmio_read_32((uint32_t)&priv->ctl->mrctrl0), mrctrl0);
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mmio_write_32((uint32_t)&priv->ctl->mrctrl1, data);
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VERBOSE("[0x%x] mrctrl1 = 0x%x\n",
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(uint32_t)&priv->ctl->mrctrl1,
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mmio_read_32((uint32_t)&priv->ctl->mrctrl1));
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mmio_write_32((uintptr_t)&priv->ctl->mrctrl0, mrctrl0);
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VERBOSE("[0x%lx] mrctrl0 = 0x%x (0x%x)\n",
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(uintptr_t)&priv->ctl->mrctrl0,
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mmio_read_32((uintptr_t)&priv->ctl->mrctrl0), mrctrl0);
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mmio_write_32((uintptr_t)&priv->ctl->mrctrl1, data);
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VERBOSE("[0x%lx] mrctrl1 = 0x%x\n",
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(uintptr_t)&priv->ctl->mrctrl1,
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mmio_read_32((uintptr_t)&priv->ctl->mrctrl1));
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/*
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* 3. In a separate APB transaction, write the MRCTRL0.mr_wr to 1. This
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@ -489,22 +518,22 @@ static void stm32mp1_mode_register_write(struct ddr_info *priv, uint8_t addr,
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* initiated until it is deasserted.
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*/
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mrctrl0 |= DDRCTRL_MRCTRL0_MR_WR;
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mmio_write_32((uint32_t)&priv->ctl->mrctrl0, mrctrl0);
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mmio_write_32((uintptr_t)&priv->ctl->mrctrl0, mrctrl0);
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while ((mmio_read_32((uint32_t)&priv->ctl->mrstat) &
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while ((mmio_read_32((uintptr_t)&priv->ctl->mrstat) &
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DDRCTRL_MRSTAT_MR_WR_BUSY) != 0U) {
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;
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}
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VERBOSE("[0x%x] mrctrl0 = 0x%x\n",
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(uint32_t)&priv->ctl->mrctrl0, mrctrl0);
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VERBOSE("[0x%lx] mrctrl0 = 0x%x\n",
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(uintptr_t)&priv->ctl->mrctrl0, mrctrl0);
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}
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/* Switch DDR3 from DLL-on to DLL-off */
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static void stm32mp1_ddr3_dll_off(struct ddr_info *priv)
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{
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uint32_t mr1 = mmio_read_32((uint32_t)&priv->phy->mr1);
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uint32_t mr2 = mmio_read_32((uint32_t)&priv->phy->mr2);
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uint32_t mr1 = mmio_read_32((uintptr_t)&priv->phy->mr1);
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uint32_t mr2 = mmio_read_32((uintptr_t)&priv->phy->mr2);
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uint32_t dbgcam;
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VERBOSE("mr1: 0x%x\n", mr1);
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@ -514,10 +543,10 @@ static void stm32mp1_ddr3_dll_off(struct ddr_info *priv)
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* 1. Set the DBG1.dis_hif = 1.
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* This prevents further reads/writes being received on the HIF.
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*/
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mmio_setbits_32((uint32_t)&priv->ctl->dbg1, DDRCTRL_DBG1_DIS_HIF);
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VERBOSE("[0x%x] dbg1 = 0x%x\n",
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(uint32_t)&priv->ctl->dbg1,
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mmio_read_32((uint32_t)&priv->ctl->dbg1));
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mmio_setbits_32((uintptr_t)&priv->ctl->dbg1, DDRCTRL_DBG1_DIS_HIF);
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VERBOSE("[0x%lx] dbg1 = 0x%x\n",
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(uintptr_t)&priv->ctl->dbg1,
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mmio_read_32((uintptr_t)&priv->ctl->dbg1));
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/*
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* 2. Ensure all commands have been flushed from the uMCTL2 by polling
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@ -528,9 +557,9 @@ static void stm32mp1_ddr3_dll_off(struct ddr_info *priv)
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* DBGCAM.dbg_hpr_q_depth = 0.
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*/
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do {
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dbgcam = mmio_read_32((uint32_t)&priv->ctl->dbgcam);
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VERBOSE("[0x%x] dbgcam = 0x%x\n",
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(uint32_t)&priv->ctl->dbgcam, dbgcam);
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dbgcam = mmio_read_32((uintptr_t)&priv->ctl->dbgcam);
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VERBOSE("[0x%lx] dbgcam = 0x%x\n",
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(uintptr_t)&priv->ctl->dbgcam, dbgcam);
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} while ((((dbgcam & DDRCTRL_DBGCAM_DATA_PIPELINE_EMPTY) ==
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DDRCTRL_DBGCAM_DATA_PIPELINE_EMPTY)) &&
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((dbgcam & DDRCTRL_DBGCAM_DBG_Q_DEPTH) == 0U));
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@ -574,11 +603,11 @@ static void stm32mp1_ddr3_dll_off(struct ddr_info *priv)
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* PWRCTL.selfref_sw = 1, and polling STAT.operating_mode to ensure
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* the DDRC has entered self-refresh.
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*/
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mmio_setbits_32((uint32_t)&priv->ctl->pwrctl,
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mmio_setbits_32((uintptr_t)&priv->ctl->pwrctl,
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DDRCTRL_PWRCTL_SELFREF_SW);
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VERBOSE("[0x%x] pwrctl = 0x%x\n",
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(uint32_t)&priv->ctl->pwrctl,
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mmio_read_32((uint32_t)&priv->ctl->pwrctl));
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VERBOSE("[0x%lx] pwrctl = 0x%x\n",
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(uintptr_t)&priv->ctl->pwrctl,
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mmio_read_32((uintptr_t)&priv->ctl->pwrctl));
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/*
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* 8. Wait until STAT.operating_mode[1:0]==11 indicating that the
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@ -594,10 +623,10 @@ static void stm32mp1_ddr3_dll_off(struct ddr_info *priv)
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*/
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stm32mp1_start_sw_done(priv->ctl);
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|
||||
mmio_setbits_32((uint32_t)&priv->ctl->mstr, DDRCTRL_MSTR_DLL_OFF_MODE);
|
||||
VERBOSE("[0x%x] mstr = 0x%x\n",
|
||||
(uint32_t)&priv->ctl->mstr,
|
||||
mmio_read_32((uint32_t)&priv->ctl->mstr));
|
||||
mmio_setbits_32((uintptr_t)&priv->ctl->mstr, DDRCTRL_MSTR_DLL_OFF_MODE);
|
||||
VERBOSE("[0x%lx] mstr = 0x%x\n",
|
||||
(uintptr_t)&priv->ctl->mstr,
|
||||
mmio_read_32((uintptr_t)&priv->ctl->mstr));
|
||||
|
||||
stm32mp1_wait_sw_done_ack(priv->ctl);
|
||||
|
||||
|
|
@ -611,26 +640,26 @@ static void stm32mp1_ddr3_dll_off(struct ddr_info *priv)
|
|||
|
||||
/* Change Bypass Mode Frequency Range */
|
||||
if (stm32mp1_clk_get_rate(DDRPHYC) < 100000000U) {
|
||||
mmio_clrbits_32((uint32_t)&priv->phy->dllgcr,
|
||||
mmio_clrbits_32((uintptr_t)&priv->phy->dllgcr,
|
||||
DDRPHYC_DLLGCR_BPS200);
|
||||
} else {
|
||||
mmio_setbits_32((uint32_t)&priv->phy->dllgcr,
|
||||
mmio_setbits_32((uintptr_t)&priv->phy->dllgcr,
|
||||
DDRPHYC_DLLGCR_BPS200);
|
||||
}
|
||||
|
||||
mmio_setbits_32((uint32_t)&priv->phy->acdllcr, DDRPHYC_ACDLLCR_DLLDIS);
|
||||
mmio_setbits_32((uintptr_t)&priv->phy->acdllcr, DDRPHYC_ACDLLCR_DLLDIS);
|
||||
|
||||
mmio_setbits_32((uint32_t)&priv->phy->dx0dllcr,
|
||||
mmio_setbits_32((uintptr_t)&priv->phy->dx0dllcr,
|
||||
DDRPHYC_DXNDLLCR_DLLDIS);
|
||||
mmio_setbits_32((uint32_t)&priv->phy->dx1dllcr,
|
||||
mmio_setbits_32((uintptr_t)&priv->phy->dx1dllcr,
|
||||
DDRPHYC_DXNDLLCR_DLLDIS);
|
||||
mmio_setbits_32((uint32_t)&priv->phy->dx2dllcr,
|
||||
mmio_setbits_32((uintptr_t)&priv->phy->dx2dllcr,
|
||||
DDRPHYC_DXNDLLCR_DLLDIS);
|
||||
mmio_setbits_32((uint32_t)&priv->phy->dx3dllcr,
|
||||
mmio_setbits_32((uintptr_t)&priv->phy->dx3dllcr,
|
||||
DDRPHYC_DXNDLLCR_DLLDIS);
|
||||
|
||||
/* 12. Exit the self-refresh state by setting PWRCTL.selfref_sw = 0. */
|
||||
mmio_clrbits_32((uint32_t)&priv->ctl->pwrctl,
|
||||
mmio_clrbits_32((uintptr_t)&priv->ctl->pwrctl,
|
||||
DDRCTRL_PWRCTL_SELFREF_SW);
|
||||
stm32mp1_wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_NORMAL);
|
||||
|
||||
|
|
@ -646,20 +675,20 @@ static void stm32mp1_ddr3_dll_off(struct ddr_info *priv)
|
|||
*/
|
||||
|
||||
/* 15. Write DBG1.dis_hif = 0 to re-enable reads and writes. */
|
||||
mmio_clrbits_32((uint32_t)&priv->ctl->dbg1, DDRCTRL_DBG1_DIS_HIF);
|
||||
VERBOSE("[0x%x] dbg1 = 0x%x\n",
|
||||
(uint32_t)&priv->ctl->dbg1,
|
||||
mmio_read_32((uint32_t)&priv->ctl->dbg1));
|
||||
mmio_clrbits_32((uintptr_t)&priv->ctl->dbg1, DDRCTRL_DBG1_DIS_HIF);
|
||||
VERBOSE("[0x%lx] dbg1 = 0x%x\n",
|
||||
(uintptr_t)&priv->ctl->dbg1,
|
||||
mmio_read_32((uintptr_t)&priv->ctl->dbg1));
|
||||
}
|
||||
|
||||
static void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl)
|
||||
{
|
||||
stm32mp1_start_sw_done(ctl);
|
||||
/* Quasi-dynamic register update*/
|
||||
mmio_setbits_32((uint32_t)&ctl->rfshctl3,
|
||||
mmio_setbits_32((uintptr_t)&ctl->rfshctl3,
|
||||
DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH);
|
||||
mmio_clrbits_32((uint32_t)&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN);
|
||||
mmio_clrbits_32((uint32_t)&ctl->dfimisc,
|
||||
mmio_clrbits_32((uintptr_t)&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN);
|
||||
mmio_clrbits_32((uintptr_t)&ctl->dfimisc,
|
||||
DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
|
||||
stm32mp1_wait_sw_done_ack(ctl);
|
||||
}
|
||||
|
|
@ -669,14 +698,14 @@ static void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl,
|
|||
{
|
||||
stm32mp1_start_sw_done(ctl);
|
||||
if ((rfshctl3 & DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH) == 0U) {
|
||||
mmio_clrbits_32((uint32_t)&ctl->rfshctl3,
|
||||
mmio_clrbits_32((uintptr_t)&ctl->rfshctl3,
|
||||
DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH);
|
||||
}
|
||||
if ((pwrctl & DDRCTRL_PWRCTL_POWERDOWN_EN) != 0U) {
|
||||
mmio_setbits_32((uint32_t)&ctl->pwrctl,
|
||||
mmio_setbits_32((uintptr_t)&ctl->pwrctl,
|
||||
DDRCTRL_PWRCTL_POWERDOWN_EN);
|
||||
}
|
||||
mmio_setbits_32((uint32_t)&ctl->dfimisc,
|
||||
mmio_setbits_32((uintptr_t)&ctl->dfimisc,
|
||||
DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
|
||||
stm32mp1_wait_sw_done_ack(ctl);
|
||||
}
|
||||
|
|
@ -694,12 +723,14 @@ void stm32mp1_ddr_init(struct ddr_info *priv,
|
|||
struct stm32mp1_ddr_config *config)
|
||||
{
|
||||
uint32_t pir;
|
||||
int ret;
|
||||
int ret = -EINVAL;
|
||||
|
||||
if ((config->c_reg.mstr & DDRCTRL_MSTR_DDR3) != 0U) {
|
||||
ret = board_ddr_power_init(STM32MP_DDR3);
|
||||
} else {
|
||||
} else if ((config->c_reg.mstr & DDRCTRL_MSTR_LPDDR2) != 0U) {
|
||||
ret = board_ddr_power_init(STM32MP_LPDDR2);
|
||||
} else {
|
||||
ERROR("DDR type not supported\n");
|
||||
}
|
||||
|
||||
if (ret != 0) {
|
||||
|
|
@ -746,11 +777,11 @@ void stm32mp1_ddr_init(struct ddr_info *priv,
|
|||
|
||||
/* 1.5. initialize registers ddr_umctl2 */
|
||||
/* Stop uMCTL2 before PHY is ready */
|
||||
mmio_clrbits_32((uint32_t)&priv->ctl->dfimisc,
|
||||
mmio_clrbits_32((uintptr_t)&priv->ctl->dfimisc,
|
||||
DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
|
||||
VERBOSE("[0x%x] dfimisc = 0x%x\n",
|
||||
(uint32_t)&priv->ctl->dfimisc,
|
||||
mmio_read_32((uint32_t)&priv->ctl->dfimisc));
|
||||
VERBOSE("[0x%lx] dfimisc = 0x%x\n",
|
||||
(uintptr_t)&priv->ctl->dfimisc,
|
||||
mmio_read_32((uintptr_t)&priv->ctl->dfimisc));
|
||||
|
||||
set_reg(priv, REG_REG, &config->c_reg);
|
||||
|
||||
|
|
@ -759,23 +790,23 @@ void stm32mp1_ddr_init(struct ddr_info *priv,
|
|||
(DDRCTRL_MSTR_DDR3 | DDRCTRL_MSTR_DLL_OFF_MODE))
|
||||
== (DDRCTRL_MSTR_DDR3 | DDRCTRL_MSTR_DLL_OFF_MODE)) {
|
||||
VERBOSE("deactivate DLL OFF in mstr\n");
|
||||
mmio_clrbits_32((uint32_t)&priv->ctl->mstr,
|
||||
mmio_clrbits_32((uintptr_t)&priv->ctl->mstr,
|
||||
DDRCTRL_MSTR_DLL_OFF_MODE);
|
||||
VERBOSE("[0x%x] mstr = 0x%x\n",
|
||||
(uint32_t)&priv->ctl->mstr,
|
||||
mmio_read_32((uint32_t)&priv->ctl->mstr));
|
||||
VERBOSE("[0x%lx] mstr = 0x%x\n",
|
||||
(uintptr_t)&priv->ctl->mstr,
|
||||
mmio_read_32((uintptr_t)&priv->ctl->mstr));
|
||||
}
|
||||
|
||||
set_reg(priv, REG_TIMING, &config->c_timing);
|
||||
set_reg(priv, REG_MAP, &config->c_map);
|
||||
|
||||
/* Skip CTRL init, SDRAM init is done by PHY PUBL */
|
||||
mmio_clrsetbits_32((uint32_t)&priv->ctl->init0,
|
||||
mmio_clrsetbits_32((uintptr_t)&priv->ctl->init0,
|
||||
DDRCTRL_INIT0_SKIP_DRAM_INIT_MASK,
|
||||
DDRCTRL_INIT0_SKIP_DRAM_INIT_NORMAL);
|
||||
VERBOSE("[0x%x] init0 = 0x%x\n",
|
||||
(uint32_t)&priv->ctl->init0,
|
||||
mmio_read_32((uint32_t)&priv->ctl->init0));
|
||||
VERBOSE("[0x%lx] init0 = 0x%x\n",
|
||||
(uintptr_t)&priv->ctl->init0,
|
||||
mmio_read_32((uintptr_t)&priv->ctl->init0));
|
||||
|
||||
set_reg(priv, REG_PERF, &config->c_perf);
|
||||
|
||||
|
|
@ -797,10 +828,10 @@ void stm32mp1_ddr_init(struct ddr_info *priv,
|
|||
(DDRCTRL_MSTR_DDR3 | DDRCTRL_MSTR_DLL_OFF_MODE))
|
||||
== (DDRCTRL_MSTR_DDR3 | DDRCTRL_MSTR_DLL_OFF_MODE)) {
|
||||
VERBOSE("deactivate DLL OFF in mr1\n");
|
||||
mmio_clrbits_32((uint32_t)&priv->phy->mr1, BIT(0));
|
||||
VERBOSE("[0x%x] mr1 = 0x%x\n",
|
||||
(uint32_t)&priv->phy->mr1,
|
||||
mmio_read_32((uint32_t)&priv->phy->mr1));
|
||||
mmio_clrbits_32((uintptr_t)&priv->phy->mr1, BIT(0));
|
||||
VERBOSE("[0x%lx] mr1 = 0x%x\n",
|
||||
(uintptr_t)&priv->phy->mr1,
|
||||
mmio_read_32((uintptr_t)&priv->phy->mr1));
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -830,11 +861,11 @@ void stm32mp1_ddr_init(struct ddr_info *priv,
|
|||
*/
|
||||
stm32mp1_start_sw_done(priv->ctl);
|
||||
|
||||
mmio_setbits_32((uint32_t)&priv->ctl->dfimisc,
|
||||
mmio_setbits_32((uintptr_t)&priv->ctl->dfimisc,
|
||||
DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
|
||||
VERBOSE("[0x%x] dfimisc = 0x%x\n",
|
||||
(uint32_t)&priv->ctl->dfimisc,
|
||||
mmio_read_32((uint32_t)&priv->ctl->dfimisc));
|
||||
VERBOSE("[0x%lx] dfimisc = 0x%x\n",
|
||||
(uintptr_t)&priv->ctl->dfimisc,
|
||||
mmio_read_32((uintptr_t)&priv->ctl->dfimisc));
|
||||
|
||||
stm32mp1_wait_sw_done_ack(priv->ctl);
|
||||
|
||||
|
|
@ -884,14 +915,16 @@ void stm32mp1_ddr_init(struct ddr_info *priv,
|
|||
config->c_reg.pwrctl);
|
||||
|
||||
/* Enable uMCTL2 AXI port 0 */
|
||||
mmio_setbits_32((uint32_t)&priv->ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN);
|
||||
VERBOSE("[0x%x] pctrl_0 = 0x%x\n",
|
||||
(uint32_t)&priv->ctl->pctrl_0,
|
||||
mmio_read_32((uint32_t)&priv->ctl->pctrl_0));
|
||||
mmio_setbits_32((uintptr_t)&priv->ctl->pctrl_0,
|
||||
DDRCTRL_PCTRL_N_PORT_EN);
|
||||
VERBOSE("[0x%lx] pctrl_0 = 0x%x\n",
|
||||
(uintptr_t)&priv->ctl->pctrl_0,
|
||||
mmio_read_32((uintptr_t)&priv->ctl->pctrl_0));
|
||||
|
||||
/* Enable uMCTL2 AXI port 1 */
|
||||
mmio_setbits_32((uint32_t)&priv->ctl->pctrl_1, DDRCTRL_PCTRL_N_PORT_EN);
|
||||
VERBOSE("[0x%x] pctrl_1 = 0x%x\n",
|
||||
(uint32_t)&priv->ctl->pctrl_1,
|
||||
mmio_read_32((uint32_t)&priv->ctl->pctrl_1));
|
||||
mmio_setbits_32((uintptr_t)&priv->ctl->pctrl_1,
|
||||
DDRCTRL_PCTRL_N_PORT_EN);
|
||||
VERBOSE("[0x%lx] pctrl_1 = 0x%x\n",
|
||||
(uintptr_t)&priv->ctl->pctrl_1,
|
||||
mmio_read_32((uintptr_t)&priv->ctl->pctrl_1));
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue