mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-22 04:24:19 +00:00
refactor(cpus): convert Cortex-A35 to use the errata framework
This involves replacing: * the reset_func with the standard cpu_reset_func_{start,end} to apply errata automatically * the <cpu>_errata_report with the errata_report_shim to report errata automatically ...and for each erratum: * the prologue with the workaround_<type>_start to do the checks and framework registration automatically * the epilogue with the workaround_<type>_end * the checker function with the check_erratum_<type> to make it more descriptive It is important to note that the errata workaround and checking sequences remain unchanged and preserve their git blame. Testing was conducted by: * Manual comparison of disassembly of converted functions with non- converted functions. aarch64-none-elf-objdump -D <TF-A with conversion>/build/../release/bl31/bl31.elf vs aarch64-none-elf-objdump -D <TF-A with clean repo>/build/fvp/release/bl31/bl31.elf * Build for release with all errata flags enabled and ensure the changes were identical. CROSS_COMPILE=aarch64-none-elf- make PLAT=fvp \ DEBUG=0 HW_ASSISTED_COHERENCY=0 \ BL33=<tf-a-tests>/build/fvp/debug/tftf.bin \ all fip ERRATA_A35_855472=1 * Build for debug with all errata enabled and step through ArmDS at reset to ensure all functions are entered. Change-Id: Ib001e9fc269e60369ccfda0245a3e6247f0d6aaa Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
This commit is contained in:
parent
db8621a2fe
commit
40eef67e6e
1 changed files with 7 additions and 57 deletions
|
@ -1,5 +1,5 @@
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
|
* Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
*/
|
*/
|
||||||
|
@ -36,47 +36,19 @@ func cortex_a35_disable_smp
|
||||||
ret
|
ret
|
||||||
endfunc cortex_a35_disable_smp
|
endfunc cortex_a35_disable_smp
|
||||||
|
|
||||||
/* ---------------------------------------------------
|
workaround_reset_start cortex_a35, ERRATUM(855472), ERRATA_A35_855472
|
||||||
* Errata Workaround for Cortex A35 Errata #855472.
|
|
||||||
* This applies to revisions r0p0 of Cortex A35.
|
|
||||||
* Inputs:
|
|
||||||
* x0: variant[4:7] and revision[0:3] of current cpu.
|
|
||||||
* Shall clobber: x0-x17
|
|
||||||
* ---------------------------------------------------
|
|
||||||
*/
|
|
||||||
func errata_a35_855472_wa
|
|
||||||
/*
|
|
||||||
* Compare x0 against revision r0p0
|
|
||||||
*/
|
|
||||||
mov x17, x30
|
|
||||||
bl check_errata_855472
|
|
||||||
cbz x0, 1f
|
|
||||||
mrs x1, CORTEX_A35_CPUACTLR_EL1
|
mrs x1, CORTEX_A35_CPUACTLR_EL1
|
||||||
orr x1, x1, #CORTEX_A35_CPUACTLR_EL1_ENDCCASCI
|
orr x1, x1, #CORTEX_A35_CPUACTLR_EL1_ENDCCASCI
|
||||||
msr CORTEX_A35_CPUACTLR_EL1, x1
|
msr CORTEX_A35_CPUACTLR_EL1, x1
|
||||||
isb
|
workaround_reset_end cortex_a35, ERRATUM(855472)
|
||||||
1:
|
|
||||||
ret x17
|
|
||||||
endfunc errata_a35_855472_wa
|
|
||||||
|
|
||||||
func check_errata_855472
|
check_erratum_ls cortex_a35, ERRATUM(855472), CPU_REV(0, 0)
|
||||||
mov x1, #0x00
|
|
||||||
b cpu_rev_var_ls
|
|
||||||
endfunc check_errata_855472
|
|
||||||
|
|
||||||
/* -------------------------------------------------
|
/* -------------------------------------------------
|
||||||
* The CPU Ops reset function for Cortex-A35.
|
* The CPU Ops reset function for Cortex-A35.
|
||||||
* Clobbers: x0
|
|
||||||
* -------------------------------------------------
|
* -------------------------------------------------
|
||||||
*/
|
*/
|
||||||
func cortex_a35_reset_func
|
cpu_reset_func_start cortex_a35
|
||||||
mov x19, x30
|
|
||||||
bl cpu_get_rev_var
|
|
||||||
|
|
||||||
#if ERRATA_A35_855472
|
|
||||||
bl errata_a35_855472_wa
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* ---------------------------------------------
|
/* ---------------------------------------------
|
||||||
* Enable the SMP bit.
|
* Enable the SMP bit.
|
||||||
* ---------------------------------------------
|
* ---------------------------------------------
|
||||||
|
@ -84,9 +56,7 @@ func cortex_a35_reset_func
|
||||||
mrs x0, CORTEX_A35_CPUECTLR_EL1
|
mrs x0, CORTEX_A35_CPUECTLR_EL1
|
||||||
orr x0, x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT
|
orr x0, x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT
|
||||||
msr CORTEX_A35_CPUECTLR_EL1, x0
|
msr CORTEX_A35_CPUECTLR_EL1, x0
|
||||||
isb
|
cpu_reset_func_end cortex_a35
|
||||||
ret x19
|
|
||||||
endfunc cortex_a35_reset_func
|
|
||||||
|
|
||||||
func cortex_a35_core_pwr_dwn
|
func cortex_a35_core_pwr_dwn
|
||||||
mov x18, x30
|
mov x18, x30
|
||||||
|
@ -149,27 +119,7 @@ func cortex_a35_cluster_pwr_dwn
|
||||||
b cortex_a35_disable_smp
|
b cortex_a35_disable_smp
|
||||||
endfunc cortex_a35_cluster_pwr_dwn
|
endfunc cortex_a35_cluster_pwr_dwn
|
||||||
|
|
||||||
#if REPORT_ERRATA
|
errata_report_shim cortex_a35
|
||||||
/*
|
|
||||||
* Errata printing function for Cortex A35. Must follow AAPCS.
|
|
||||||
*/
|
|
||||||
func cortex_a35_errata_report
|
|
||||||
stp x8, x30, [sp, #-16]!
|
|
||||||
|
|
||||||
bl cpu_get_rev_var
|
|
||||||
mov x8, x0
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Report all errata. The revision-variant information is passed to
|
|
||||||
* checking functions of each errata.
|
|
||||||
*/
|
|
||||||
report_errata ERRATA_A35_855472, cortex_a35, 855472
|
|
||||||
|
|
||||||
ldp x8, x30, [sp], #16
|
|
||||||
ret
|
|
||||||
endfunc cortex_a35_errata_report
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
/* ---------------------------------------------
|
/* ---------------------------------------------
|
||||||
* This function provides cortex_a35 specific
|
* This function provides cortex_a35 specific
|
||||||
|
|
Loading…
Add table
Reference in a new issue