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https://github.com/ARM-software/arm-trusted-firmware.git
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feat(context-mgmt): introduce EL3/root context
* This patch adds root context procedure to restore/configure
the registers, which are of importance during EL3 execution.
* EL3/Root context is a simple restore operation that overwrites
the following bits: (MDCR_EL3.SDD, SCR_EL3.{EA, SIF}, PMCR_EL0.DP
PSTATE.DIT) while the execution is in EL3.
* It ensures EL3 world maintains its own settings distinct
from other worlds (NS/Realm/SWd). With this in place, the EL3
system register settings is no longer influenced by settings of
incoming worlds. This allows the EL3/Root world to access features
for its own execution at EL3 (eg: Pauth).
* It should be invoked at cold and warm boot entry paths and also
at all the possible exception handlers routing to EL3 at runtime.
Cold and warm boot paths are handled by including setup_el3_context
function in "el3_entrypoint_common" macro, which gets invoked in
both the entry paths.
* At runtime, el3_context is setup at the stage, while we get prepared
to enter into EL3 via "prepare_el3_entry" routine.
Change-Id: I5c090978c54a53bc1c119d1bc5fa77cd8813cdc2
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
This commit is contained in:
Jayanth Dodderi Chidanand
parent
742d0e6ef3
commit
40e5f7a58f
3 changed files with 77 additions and 62 deletions
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@ -229,7 +229,6 @@ vector_entry sync_exception_aarch64
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save_x30
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apply_at_speculative_wa
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sync_and_handle_pending_serror
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unmask_async_ea
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handle_sync_exception
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end_vector_entry sync_exception_aarch64
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@ -237,7 +236,6 @@ vector_entry irq_aarch64
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save_x30
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apply_at_speculative_wa
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sync_and_handle_pending_serror
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unmask_async_ea
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b handle_interrupt_exception
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end_vector_entry irq_aarch64
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@ -245,7 +243,6 @@ vector_entry fiq_aarch64
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save_x30
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apply_at_speculative_wa
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sync_and_handle_pending_serror
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unmask_async_ea
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b handle_interrupt_exception
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end_vector_entry fiq_aarch64
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@ -258,7 +255,6 @@ vector_entry serror_aarch64
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save_x30
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apply_at_speculative_wa
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sync_and_handle_pending_serror
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unmask_async_ea
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b handle_lower_el_async_ea
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#else
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b report_unhandled_exception
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@ -279,7 +275,6 @@ vector_entry sync_exception_aarch32
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save_x30
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apply_at_speculative_wa
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sync_and_handle_pending_serror
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unmask_async_ea
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handle_sync_exception
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end_vector_entry sync_exception_aarch32
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@ -287,7 +282,6 @@ vector_entry irq_aarch32
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save_x30
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apply_at_speculative_wa
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sync_and_handle_pending_serror
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unmask_async_ea
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b handle_interrupt_exception
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end_vector_entry irq_aarch32
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@ -295,7 +289,6 @@ vector_entry fiq_aarch32
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save_x30
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apply_at_speculative_wa
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sync_and_handle_pending_serror
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unmask_async_ea
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b handle_interrupt_exception
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end_vector_entry fiq_aarch32
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@ -308,7 +301,6 @@ vector_entry serror_aarch32
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save_x30
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apply_at_speculative_wa
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sync_and_handle_pending_serror
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unmask_async_ea
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b handle_lower_el_async_ea
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#else
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b report_unhandled_exception
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@ -59,24 +59,18 @@
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* zero here but are updated ahead of transitioning to a lower EL in the
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* function cm_init_context_common().
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*
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* SCR_EL3.SIF: Set to one to disable instruction fetches from
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* Non-secure memory.
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*
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* SCR_EL3.EA: Set to one to route External Aborts and SError Interrupts
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* to EL3 when executing at any EL.
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*
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* SCR_EL3.EEL2: Set to one if S-EL2 is present and enabled.
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*
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* NOTE: Modifying EEL2 bit along with EA bit ensures that we mitigate
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* against ERRATA_V2_3099206.
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* ---------------------------------------------------------------------
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*/
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mov_imm x0, (SCR_RESET_VAL | SCR_EA_BIT | SCR_SIF_BIT)
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mov_imm x0, SCR_RESET_VAL
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#if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2
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mrs x1, id_aa64pfr0_el1
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and x1, x1, #(ID_AA64PFR0_SEL2_MASK << ID_AA64PFR0_SEL2_SHIFT)
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cbz x1, 1f
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orr x0, x0, #SCR_EEL2_BIT
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mrs x1, id_aa64pfr0_el1
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and x1, x1, #(ID_AA64PFR0_SEL2_MASK << ID_AA64PFR0_SEL2_SHIFT)
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cbz x1, 1f
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orr x0, x0, #SCR_EEL2_BIT
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#endif
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1:
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msr scr_el3, x0
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@ -84,21 +78,10 @@
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/* ---------------------------------------------------------------------
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* Initialise MDCR_EL3, setting all fields rather than relying on hw.
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* Some fields are architecturally UNKNOWN on reset.
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*
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* MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug.
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* Debug exceptions, other than Breakpoint Instruction exceptions, are
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* disabled from all ELs in Secure state.
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*/
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mov_imm x0, (MDCR_EL3_RESET_VAL | MDCR_SDD_BIT)
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mov_imm x0, MDCR_EL3_RESET_VAL
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msr mdcr_el3, x0
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/* ---------------------------------------------------------------------
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* Enable External Aborts and SError Interrupts now that the exception
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* vectors have been setup.
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* ---------------------------------------------------------------------
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*/
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msr daifclr, #DAIF_ABT_BIT
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/* ---------------------------------------------------------------------
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* Initialise CPTR_EL3, setting all fields rather than relying on hw.
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* All fields are architecturally UNKNOWN on reset.
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@ -107,28 +90,6 @@
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mov_imm x0, CPTR_EL3_RESET_VAL
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msr cptr_el3, x0
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/*
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* If Data Independent Timing (DIT) functionality is implemented,
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* always enable DIT in EL3.
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* First assert that the FEAT_DIT build flag matches the feature id
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* register value for DIT.
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*/
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#if ENABLE_FEAT_DIT
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#if ENABLE_ASSERTIONS || ENABLE_FEAT_DIT > 1
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mrs x0, id_aa64pfr0_el1
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ubfx x0, x0, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH
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#if ENABLE_FEAT_DIT > 1
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cbz x0, 1f
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#else
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cmp x0, #DIT_IMPLEMENTED
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ASM_ASSERT(eq)
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#endif
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#endif /* ENABLE_ASSERTIONS */
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mov x0, #DIT_BIT
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msr DIT, x0
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1:
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#endif
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.endm
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/* -----------------------------------------------------------------------------
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@ -270,6 +231,12 @@
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el3_arch_init_common
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/* ---------------------------------------------------------------------
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* Set the el3 execution context(i.e. root_context).
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* ---------------------------------------------------------------------
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*/
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setup_el3_execution_context
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.if \_secondary_cold_boot
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/* -------------------------------------------------------------
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* Check if this is a primary or secondary CPU cold boot.
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@ -460,4 +427,68 @@
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end:
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.endm
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/*-----------------------------------------------------------------------------
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* Helper macro to configure EL3 registers we care about, while executing
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* at EL3/Root world. Root world has its own execution environment and
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* needs to have its settings configured to be independent of other worlds.
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* -----------------------------------------------------------------------------
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*/
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.macro setup_el3_execution_context
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/* ---------------------------------------------------------------------
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* The following registers need to be part of separate root context
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* as their values are of importance during EL3 execution.
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* Hence these registers are overwritten to their intital values,
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* irrespective of whichever world they return from to ensure EL3 has a
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* consistent execution context throughout the lifetime of TF-A.
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*
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* DAIF.A: Enable External Aborts and SError Interrupts at EL3.
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*
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* MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug.
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* Debug exceptions, other than Breakpoint Instruction exceptions, are
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* disabled from all ELs in Secure state.
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*
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* SCR_EL3.EA: Set to one to enable SError interrupts at EL3.
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*
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* SCR_EL3.SIF: Set to one to disable instruction fetches from
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* Non-secure memory.
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*
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* PMCR_EL0.DP: Set to one so that the cycle counter,
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* PMCCNTR_EL0 does not count when event counting is prohibited.
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* Necessary on PMUv3 <= p7 where MDCR_EL3.{SCCD,MCCD} are not
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* available.
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*
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* PSTATE.DIT: Set to one to enable the Data Independent Timing (DIT)
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* functionality, if implemented in EL3.
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* ---------------------------------------------------------------------
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*/
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msr daifclr, #DAIF_ABT_BIT
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mrs x15, mdcr_el3
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orr x15, x15, #MDCR_SDD_BIT
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msr mdcr_el3, x15
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mrs x15, scr_el3
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orr x15, x15, #SCR_EA_BIT
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orr x15, x15, #SCR_SIF_BIT
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msr scr_el3, x15
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mrs x15, pmcr_el0
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orr x15, x15, #PMCR_EL0_DP_BIT
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msr pmcr_el0, x15
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#if ENABLE_FEAT_DIT
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#if ENABLE_FEAT_DIT > 1
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mrs x15, id_aa64pfr0_el1
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ubfx x15, x15, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH
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cbz x15, 1f
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#endif
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mov x15, #DIT_BIT
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msr DIT, x15
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1:
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#endif
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isb
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.endm
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#endif /* EL3_COMMON_MACROS_S */
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@ -400,9 +400,6 @@ no_mpam:
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/* PMUv3 is presumed to be always present */
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mrs x9, pmcr_el0
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str x9, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0]
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/* Disable cycle counter when event counting is prohibited */
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orr x9, x9, #PMCR_EL0_DP_BIT
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msr pmcr_el0, x9
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isb
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#if CTX_INCLUDE_PAUTH_REGS
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/* ----------------------------------------------------------
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@ -444,12 +441,7 @@ no_mpam:
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*/
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func prepare_el3_entry
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save_gp_pmcr_pauth_regs
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enable_serror_at_el3
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/*
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* Set the PSTATE bits not described in the Aarch64.TakeException
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* pseudocode to their default values.
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*/
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set_unset_pstate_bits
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setup_el3_execution_context
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ret
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endfunc prepare_el3_entry
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