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Merge pull request #233 from jcastillo-arm/jc/tf-issues/254
Juno: Add support for image overlaying in Trusted SRAM
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danh-arm
commit
408b79b81a
3 changed files with 100 additions and 63 deletions
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@ -1270,9 +1270,40 @@ diagrams.
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Loading the TSP image in Trusted DRAM doesn't change the memory layout of the
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other boot loader images in Trusted SRAM.
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#### Memory layout on Juno ARM development platform
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**TSP in Trusted SRAM (default option):**
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The following list describes the memory layout on Juno:
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* Trusted SRAM at 0x04000000 contains the MHU page, BL1 r/w section, BL2
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image, BL3-1 image and, optionally, the BL3-2 image.
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* The MHU 4 KB page is used as communication channel between SCP and AP. It
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also contains the entrypoint mailboxes for the AP. Mailboxes are stored in
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the first 128 bytes of the MHU page.
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* BL1 resides in flash memory at address `0x0BEC0000`. Its read-write data
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section is relocated to the top of the Trusted SRAM at runtime.
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* BL3-1 is loaded at the top of the Trusted SRAM, such that its NOBITS
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sections will overwrite BL1 R/W data. This implies that BL1 global variables
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will remain valid only until execution reaches the BL3-1 entry point during
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a cold boot.
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* BL2 is loaded below BL3-1.
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* BL3-0 is loaded temporarily into the BL3-1 memory region and transfered to
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the SCP before being overwritten by BL3-1.
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* The BL3-2 image is optional and can be loaded into one of these two
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locations: Trusted SRAM (right after the MHU page) or DRAM (14 MB starting
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at 0xFF000000 and secured by the TrustZone controller). When loaded into
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Trusted SRAM, its NOBITS sections are allowed to overlap BL2.
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Depending on the location of the BL3-2 image, it will result in different memory
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maps, illustrated by the following diagrams.
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**BL3-2 in Trusted SRAM (default option):**
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Flash0
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0x0C000000 +----------+
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@ -1281,30 +1312,30 @@ other boot loader images in Trusted SRAM.
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| BL1 (ro) |
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0x0BEC0000 |----------|
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: :
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| Bypass |
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0x08000000 +----------+
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Trusted SRAM
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0x04040000 +----------+
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| BL2 | BL3-1 is loaded
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0x04033000 |----------| after BL3-0 has
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| BL3-2 | been sent to SCP
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0x04023000 |----------| ------------------
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| BL3-0 | <<<<<<<<<<<<< | BL3-1 |
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0x04009000 |----------| ------------------
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| BL1 (rw) |
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0x04001000 |----------|
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0x08000000 +----------+ BL3-1 is loaded
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after BL3-0 has
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Trusted SRAM been sent to SCP
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0x04040000 +----------+ loaded by BL2 ------------------
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| BL1 (rw) | <<<<<<<<<<<<< | BL3-1 NOBITS |
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|----------| <<<<<<<<<<<<< |----------------|
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| BL3-0 | <<<<<<<<<<<<< | BL3-1 PROGBITS |
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|----------| ------------------
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| BL2 | <<<<<<<<<<<<< | BL3-2 NOBITS |
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|----------| <<<<<<<<<<<<< |----------------|
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| | <<<<<<<<<<<<< | BL3-2 PROGBITS |
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0x04001000 +----------+ ------------------
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| MHU |
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0x04000000 +----------+
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**TSP in the secure region of DRAM:**
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**BL3-2 in the secure region of DRAM:**
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DRAM
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0xFFE00000 +----------+
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| BL3-2 |
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| BL3-2 | (secure)
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0xFF000000 |----------|
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: :
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: : (non-secure)
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0x80000000 +----------+
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@ -1315,29 +1346,23 @@ other boot loader images in Trusted SRAM.
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| BL1 (ro) |
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0x0BEC0000 |----------|
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: :
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| Bypass |
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0x08000000 +----------+
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Trusted SRAM
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0x04040000 +----------+
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| BL2 | BL3-1 is loaded
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0x04033000 |----------| after BL3-0 has
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| | been sent to SCP
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0x04023000 |----------| ------------------
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| BL3-0 | <<<<<<<<<<<<< | BL3-1 |
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0x04009000 |----------| ------------------
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| BL1 (rw) |
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0x04001000 |----------|
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0x08000000 +----------+ BL3-1 is loaded
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after BL3-0 has
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Trusted SRAM been sent to SCP
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0x04040000 +----------+ loaded by BL2 ------------------
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| BL1 (rw) | <<<<<<<<<<<<< | BL3-1 NOBITS |
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|----------| <<<<<<<<<<<<< |----------------|
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| BL3-0 | <<<<<<<<<<<<< | BL3-1 PROGBITS |
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|----------| ------------------
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| BL2 |
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|----------|
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| |
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0x04001000 +----------+
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| MHU |
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0x04000000 +----------+
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The Message Handling Unit (MHU) page contains the entrypoint mailboxes and a
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shared memory area. This shared memory is used as a communication channel
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between the AP and the SCP.
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BL1 code starts at `0x0BEC0000`. The BL1 data section is copied to trusted SRAM
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at `0x04001000`, right after the MHU page. Entrypoint mailboxes are stored in
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the first 128 bytes of the MHU page.
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Loading the BL3-2 image in DRAM doesn't change the memory layout of the other
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images in Trusted SRAM.
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9. Firmware Image Package (FIP)
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@ -75,24 +75,6 @@
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#define MAX_IO_DEVICES 3
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#define MAX_IO_HANDLES 4
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/*******************************************************************************
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* Platform memory map related constants
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******************************************************************************/
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#define FLASH_BASE 0x08000000
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#define FLASH_SIZE 0x04000000
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/* Bypass offset from start of NOR flash */
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#define BL1_ROM_BYPASS_OFFSET 0x03EC0000
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#ifndef TZROM_BASE
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/* Use the bypass address */
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#define TZROM_BASE FLASH_BASE + BL1_ROM_BYPASS_OFFSET
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#endif
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#define TZROM_SIZE 0x00010000
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#define TZRAM_BASE 0x04001000
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#define TZRAM_SIZE 0x0003F000
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/*******************************************************************************
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* BL1 specific defines.
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* BL1 RW data is relocated from ROM to RAM at runtime so we need 2 base
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@ -100,14 +82,23 @@
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******************************************************************************/
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#define BL1_RO_BASE TZROM_BASE
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#define BL1_RO_LIMIT (TZROM_BASE + TZROM_SIZE)
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#define BL1_RW_BASE TZRAM_BASE
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#define BL1_RW_LIMIT BL31_BASE
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/*
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* Put BL1 RW at the top of the Trusted SRAM. BL1_RW_BASE is calculated using
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* the current BL1 RW debug size plus a little space for growth.
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*/
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#define BL1_RW_BASE (TZRAM_BASE + TZRAM_SIZE - 0x6000)
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#define BL1_RW_LIMIT (TZRAM_BASE + TZRAM_SIZE)
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/*******************************************************************************
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* BL2 specific defines.
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******************************************************************************/
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#define BL2_BASE (TZRAM_BASE + TZRAM_SIZE - 0xd000)
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#define BL2_LIMIT (TZRAM_BASE + TZRAM_SIZE)
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/*
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* Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
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* size plus a little space for growth.
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*/
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#define BL2_BASE (BL31_BASE - 0xC000)
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#define BL2_LIMIT BL31_BASE
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/*******************************************************************************
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* Load address of BL3-0 in the Juno port
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@ -119,8 +110,13 @@
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/*******************************************************************************
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* BL3-1 specific defines.
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******************************************************************************/
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#define BL31_BASE (TZRAM_BASE + 0x8000)
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#define BL31_LIMIT BL32_BASE
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/*
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* Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
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* current BL3-1 debug size plus a little space for growth.
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*/
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#define BL31_BASE (TZRAM_BASE + TZRAM_SIZE - 0x1D000)
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#define BL31_PROGBITS_LIMIT BL1_RW_BASE
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#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
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/*******************************************************************************
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* BL3-2 specific defines.
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@ -128,8 +124,9 @@
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#if (PLAT_TSP_LOCATION_ID == PLAT_TRUSTED_SRAM_ID)
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# define TSP_SEC_MEM_BASE TZRAM_BASE
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# define TSP_SEC_MEM_SIZE TZRAM_SIZE
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# define BL32_BASE (TZRAM_BASE + TZRAM_SIZE - 0x1d000)
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# define BL32_LIMIT BL2_BASE
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# define BL32_BASE TZRAM_BASE
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# define BL32_LIMIT BL31_BASE
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# define BL32_PROGBITS_LIMIT BL2_BASE
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#elif (PLAT_TSP_LOCATION_ID == PLAT_DRAM_ID)
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# define TSP_SEC_MEM_BASE DRAM_SEC_BASE
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# define TSP_SEC_MEM_SIZE (DRAM_SEC_SIZE - DRAM_SCP_SIZE)
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@ -37,6 +37,21 @@
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/*******************************************************************************
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* Juno memory map related constants
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******************************************************************************/
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#define FLASH_BASE 0x08000000
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#define FLASH_SIZE 0x04000000
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/* Bypass offset from start of NOR flash */
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#define BL1_ROM_BYPASS_OFFSET 0x03EC0000
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#ifndef TZROM_BASE
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/* Use the bypass address */
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#define TZROM_BASE FLASH_BASE + BL1_ROM_BYPASS_OFFSET
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#endif
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#define TZROM_SIZE 0x00010000
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#define TZRAM_BASE 0x04001000
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#define TZRAM_SIZE 0x0003F000
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#define PLAT_TRUSTED_SRAM_ID 0
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#define PLAT_DRAM_ID 1
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