From 3fb52e41fd4749a784b3e6b6757a89106abaea9a Mon Sep 17 00:00:00 2001 From: Ryan Everett Date: Tue, 14 May 2024 14:47:09 +0100 Subject: [PATCH] refactor(cpus): remove cpu specific errata funcs Errata printing is done directly via generic_errata_report. This commit removes the unused \_cpu\()_errata_report functions for all cores, and removes errata_func from cpu_ops. Change-Id: I04fefbde5f0ff63b1f1cd17c864557a14070d68c Signed-off-by: Ryan Everett --- include/lib/cpus/aarch32/cpu_macros.S | 22 ---------------- include/lib/cpus/aarch64/cpu_macros.S | 25 ------------------- include/lib/cpus/cpu_ops.h | 8 ++---- lib/cpus/aarch32/aem_generic.S | 10 +------- lib/cpus/aarch32/cortex_a12.S | 4 +-- lib/cpus/aarch32/cortex_a15.S | 4 +-- lib/cpus/aarch32/cortex_a17.S | 4 +-- lib/cpus/aarch32/cortex_a32.S | 4 +-- lib/cpus/aarch32/cortex_a5.S | 4 +-- lib/cpus/aarch32/cortex_a53.S | 4 +-- lib/cpus/aarch32/cortex_a57.S | 4 +-- lib/cpus/aarch32/cortex_a7.S | 4 +-- lib/cpus/aarch32/cortex_a72.S | 4 +-- lib/cpus/aarch32/cortex_a9.S | 4 +-- lib/cpus/aarch64/a64fx.S | 9 ------- lib/cpus/aarch64/aem_generic.S | 11 +------- lib/cpus/aarch64/cortex_a35.S | 4 +-- lib/cpus/aarch64/cortex_a510.S | 4 +-- lib/cpus/aarch64/cortex_a520.S | 4 +-- lib/cpus/aarch64/cortex_a53.S | 4 +-- lib/cpus/aarch64/cortex_a55.S | 4 +-- lib/cpus/aarch64/cortex_a57.S | 4 +-- lib/cpus/aarch64/cortex_a65.S | 22 +--------------- lib/cpus/aarch64/cortex_a65ae.S | 4 +-- lib/cpus/aarch64/cortex_a710.S | 4 +-- lib/cpus/aarch64/cortex_a715.S | 2 -- lib/cpus/aarch64/cortex_a72.S | 4 +-- lib/cpus/aarch64/cortex_a720.S | 2 -- lib/cpus/aarch64/cortex_a725.S | 2 -- lib/cpus/aarch64/cortex_a73.S | 5 +--- lib/cpus/aarch64/cortex_a75.S | 4 +-- lib/cpus/aarch64/cortex_a76.S | 4 +-- lib/cpus/aarch64/cortex_a76ae.S | 4 +-- lib/cpus/aarch64/cortex_a77.S | 3 +-- lib/cpus/aarch64/cortex_a78.S | 4 +-- lib/cpus/aarch64/cortex_a78_ae.S | 4 +-- lib/cpus/aarch64/cortex_a78c.S | 2 -- lib/cpus/aarch64/cortex_gelas.S | 2 -- lib/cpus/aarch64/cortex_x1.S | 2 -- lib/cpus/aarch64/cortex_x2.S | 4 +-- lib/cpus/aarch64/cortex_x3.S | 2 -- lib/cpus/aarch64/cortex_x4.S | 2 -- lib/cpus/aarch64/cortex_x925.S | 2 -- lib/cpus/aarch64/denver.S | 4 +-- lib/cpus/aarch64/generic.S | 3 +-- lib/cpus/aarch64/neoverse_e1.S | 4 +-- lib/cpus/aarch64/neoverse_n1.S | 4 +-- lib/cpus/aarch64/neoverse_n2.S | 4 +-- lib/cpus/aarch64/neoverse_n3.S | 2 -- lib/cpus/aarch64/neoverse_v1.S | 4 +-- lib/cpus/aarch64/neoverse_v2.S | 3 +-- lib/cpus/aarch64/neoverse_v3.S | 2 -- lib/cpus/aarch64/nevis.S | 4 +-- lib/cpus/aarch64/qemu_max.S | 4 +-- lib/cpus/aarch64/rainier.S | 4 +-- lib/cpus/aarch64/travis.S | 2 -- plat/qti/common/src/aarch64/qti_kryo4_gold.S | 12 +-------- .../qti/common/src/aarch64/qti_kryo4_silver.S | 13 +--------- plat/qti/common/src/aarch64/qti_kryo6_gold.S | 12 +-------- .../qti/common/src/aarch64/qti_kryo6_silver.S | 13 +--------- 60 files changed, 46 insertions(+), 281 deletions(-) diff --git a/include/lib/cpus/aarch32/cpu_macros.S b/include/lib/cpus/aarch32/cpu_macros.S index f651040f9..cfa5831fc 100644 --- a/include/lib/cpus/aarch32/cpu_macros.S +++ b/include/lib/cpus/aarch32/cpu_macros.S @@ -115,11 +115,6 @@ .popsection .endif - /* - * Mandatory errata status printing function for CPUs of - * this class. - */ - .word \_name\()_errata_report .word \_name\()_cpu_str #ifdef IMAGE_BL32 @@ -200,21 +195,4 @@ .popsection .endm -/* - * Maintain compatibility with the old scheme of "each cpu has its own reporter". - * TODO remove entirely once all cpus have been converted. This includes the - * cpu_ops entry, as print_errata_status can call this directly for all cpus - */ -.macro errata_report_shim _cpu:req - #if REPORT_ERRATA - func \_cpu\()_errata_report - push {r12, lr} - - bl generic_errata_report - - pop {r12, lr} - bx lr - endfunc \_cpu\()_errata_report - #endif -.endm #endif /* CPU_MACROS_S */ diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S index 9e08348c1..98294b96e 100644 --- a/include/lib/cpus/aarch64/cpu_macros.S +++ b/include/lib/cpus/aarch64/cpu_macros.S @@ -132,12 +132,6 @@ .popsection .endif - - /* - * Mandatory errata status printing function for CPUs of - * this class. - */ - .quad \_name\()_errata_report .quad \_name\()_cpu_str #ifdef IMAGE_BL31 @@ -579,23 +573,4 @@ endfunc \_cpu\()_reset_func .endm -/* - * Maintain compatibility with the old scheme of each cpu has its own reporting. - * TODO remove entirely once all cpus have been converted. This includes the - * cpu_ops entry, as print_errata_status can call this directly for all cpus - */ -.macro errata_report_shim _cpu:req - #if REPORT_ERRATA - func \_cpu\()_errata_report - /* normal stack frame for pretty debugging */ - stp x29, x30, [sp, #-16]! - mov x29, sp - - bl generic_errata_report - - ldp x29, x30, [sp], #16 - ret - endfunc \_cpu\()_errata_report - #endif -.endm #endif /* CPU_MACROS_S */ diff --git a/include/lib/cpus/cpu_ops.h b/include/lib/cpus/cpu_ops.h index 8b36ff124..0084189b5 100644 --- a/include/lib/cpus/cpu_ops.h +++ b/include/lib/cpus/cpu_ops.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -57,7 +57,6 @@ #define CPU_ERRATA_LIST_END_SIZE CPU_WORD_SIZE /* Fields required to print errata status */ #if REPORT_ERRATA -#define CPU_ERRATA_FUNC_SIZE CPU_WORD_SIZE #define CPU_CPU_STR_SIZE CPU_WORD_SIZE /* BL1 doesn't require mutual exclusion and printed flag. */ #if defined(IMAGE_BL31) || defined(IMAGE_BL32) @@ -68,7 +67,6 @@ #define CPU_ERRATA_PRINTED_SIZE 0 #endif /* defined(IMAGE_BL31) || defined(IMAGE_BL32) */ #else -#define CPU_ERRATA_FUNC_SIZE 0 #define CPU_CPU_STR_SIZE 0 #define CPU_ERRATA_LOCK_SIZE 0 #define CPU_ERRATA_PRINTED_SIZE 0 @@ -98,8 +96,7 @@ #endif /* __aarch64__ */ #define CPU_ERRATA_LIST_START CPU_PWR_DWN_OPS + CPU_PWR_DWN_OPS_SIZE #define CPU_ERRATA_LIST_END CPU_ERRATA_LIST_START + CPU_ERRATA_LIST_START_SIZE -#define CPU_ERRATA_FUNC CPU_ERRATA_LIST_END + CPU_ERRATA_LIST_END_SIZE -#define CPU_CPU_STR CPU_ERRATA_FUNC + CPU_ERRATA_FUNC_SIZE +#define CPU_CPU_STR CPU_ERRATA_LIST_END + CPU_ERRATA_LIST_END_SIZE #define CPU_ERRATA_LOCK CPU_CPU_STR + CPU_CPU_STR_SIZE #define CPU_ERRATA_PRINTED CPU_ERRATA_LOCK + CPU_ERRATA_LOCK_SIZE #if __aarch64__ @@ -130,7 +127,6 @@ struct cpu_ops { void *errata_list_start; void *errata_list_end; #if REPORT_ERRATA - void (*errata_func)(void); char *cpu_str; #if defined(IMAGE_BL31) || defined(IMAGE_BL32) spinlock_t *errata_lock; diff --git a/lib/cpus/aarch32/aem_generic.S b/lib/cpus/aarch32/aem_generic.S index 9f45e387a..f4dc0d172 100644 --- a/lib/cpus/aarch32/aem_generic.S +++ b/lib/cpus/aarch32/aem_generic.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -40,14 +40,6 @@ func aem_generic_cluster_pwr_dwn b dcsw_op_all endfunc aem_generic_cluster_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for AEM. Must follow AAPCS. - */ -func aem_generic_errata_report - bx lr -endfunc aem_generic_errata_report -#endif /* cpu_ops for Base AEM FVP */ declare_cpu_ops aem_generic, BASE_AEM_MIDR, CPU_NO_RESET_FUNC, \ diff --git a/lib/cpus/aarch32/cortex_a12.S b/lib/cpus/aarch32/cortex_a12.S index 8eec27cb2..b95020e66 100644 --- a/lib/cpus/aarch32/cortex_a12.S +++ b/lib/cpus/aarch32/cortex_a12.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -73,8 +73,6 @@ func cortex_a12_cluster_pwr_dwn b cortex_a12_disable_smp endfunc cortex_a12_cluster_pwr_dwn -errata_report_shim cortex_a12 - declare_cpu_ops cortex_a12, CORTEX_A12_MIDR, \ cortex_a12_reset_func, \ cortex_a12_core_pwr_dwn, \ diff --git a/lib/cpus/aarch32/cortex_a15.S b/lib/cpus/aarch32/cortex_a15.S index b41676d94..53489ad19 100644 --- a/lib/cpus/aarch32/cortex_a15.S +++ b/lib/cpus/aarch32/cortex_a15.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -172,8 +172,6 @@ func cortex_a15_cluster_pwr_dwn b cortex_a15_disable_smp endfunc cortex_a15_cluster_pwr_dwn -errata_report_shim cortex_a15 - declare_cpu_ops cortex_a15, CORTEX_A15_MIDR, \ cortex_a15_reset_func, \ cortex_a15_core_pwr_dwn, \ diff --git a/lib/cpus/aarch32/cortex_a17.S b/lib/cpus/aarch32/cortex_a17.S index 18775708a..05e96169e 100644 --- a/lib/cpus/aarch32/cortex_a17.S +++ b/lib/cpus/aarch32/cortex_a17.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -106,8 +106,6 @@ endfunc check_errata_cve_2017_5715 add_erratum_entry cortex_a17, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 -errata_report_shim cortex_a17 - func cortex_a17_reset_func mov r5, lr bl cpu_get_rev_var diff --git a/lib/cpus/aarch32/cortex_a32.S b/lib/cpus/aarch32/cortex_a32.S index d08b4ff57..c92a8c1bd 100644 --- a/lib/cpus/aarch32/cortex_a32.S +++ b/lib/cpus/aarch32/cortex_a32.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -117,8 +117,6 @@ func cortex_a32_cluster_pwr_dwn b cortex_a32_disable_smp endfunc cortex_a32_cluster_pwr_dwn -errata_report_shim cortex_a32 - declare_cpu_ops cortex_a32, CORTEX_A32_MIDR, \ cortex_a32_reset_func, \ cortex_a32_core_pwr_dwn, \ diff --git a/lib/cpus/aarch32/cortex_a5.S b/lib/cpus/aarch32/cortex_a5.S index 625ea7ba3..146eb9c52 100644 --- a/lib/cpus/aarch32/cortex_a5.S +++ b/lib/cpus/aarch32/cortex_a5.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -69,8 +69,6 @@ func cortex_a5_cluster_pwr_dwn b cortex_a5_disable_smp endfunc cortex_a5_cluster_pwr_dwn -errata_report_shim cortex_a5 - declare_cpu_ops cortex_a5, CORTEX_A5_MIDR, \ cortex_a5_reset_func, \ cortex_a5_core_pwr_dwn, \ diff --git a/lib/cpus/aarch32/cortex_a53.S b/lib/cpus/aarch32/cortex_a53.S index 89b238a6b..60be2b33c 100644 --- a/lib/cpus/aarch32/cortex_a53.S +++ b/lib/cpus/aarch32/cortex_a53.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -297,8 +297,6 @@ func cortex_a53_cluster_pwr_dwn b cortex_a53_disable_smp endfunc cortex_a53_cluster_pwr_dwn -errata_report_shim cortex_a53 - declare_cpu_ops cortex_a53, CORTEX_A53_MIDR, \ cortex_a53_reset_func, \ cortex_a53_core_pwr_dwn, \ diff --git a/lib/cpus/aarch32/cortex_a57.S b/lib/cpus/aarch32/cortex_a57.S index 1e5377b25..d563482dd 100644 --- a/lib/cpus/aarch32/cortex_a57.S +++ b/lib/cpus/aarch32/cortex_a57.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -606,8 +606,6 @@ func cortex_a57_cluster_pwr_dwn b cortex_a57_disable_ext_debug endfunc cortex_a57_cluster_pwr_dwn -errata_report_shim cortex_a57 - declare_cpu_ops cortex_a57, CORTEX_A57_MIDR, \ cortex_a57_reset_func, \ cortex_a57_core_pwr_dwn, \ diff --git a/lib/cpus/aarch32/cortex_a7.S b/lib/cpus/aarch32/cortex_a7.S index 4842ca63d..f99ae791d 100644 --- a/lib/cpus/aarch32/cortex_a7.S +++ b/lib/cpus/aarch32/cortex_a7.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -73,8 +73,6 @@ func cortex_a7_cluster_pwr_dwn b cortex_a7_disable_smp endfunc cortex_a7_cluster_pwr_dwn -errata_report_shim cortex_a7 - declare_cpu_ops cortex_a7, CORTEX_A7_MIDR, \ cortex_a7_reset_func, \ cortex_a7_core_pwr_dwn, \ diff --git a/lib/cpus/aarch32/cortex_a72.S b/lib/cpus/aarch32/cortex_a72.S index 77cf84dd9..8d399fd67 100644 --- a/lib/cpus/aarch32/cortex_a72.S +++ b/lib/cpus/aarch32/cortex_a72.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -256,8 +256,6 @@ func cortex_a72_cluster_pwr_dwn b cortex_a72_disable_ext_debug endfunc cortex_a72_cluster_pwr_dwn -errata_report_shim cortex_a72 - declare_cpu_ops cortex_a72, CORTEX_A72_MIDR, \ cortex_a72_reset_func, \ cortex_a72_core_pwr_dwn, \ diff --git a/lib/cpus/aarch32/cortex_a9.S b/lib/cpus/aarch32/cortex_a9.S index 1e9757a4f..dc5ff2703 100644 --- a/lib/cpus/aarch32/cortex_a9.S +++ b/lib/cpus/aarch32/cortex_a9.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -57,8 +57,6 @@ endfunc check_errata_cve_2017_5715 add_erratum_entry cortex_a9, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 -errata_report_shim cortex_a9 - func cortex_a9_reset_func #if IMAGE_BL32 && WORKAROUND_CVE_2017_5715 ldr r0, =wa_cve_2017_5715_bpiall_vbar diff --git a/lib/cpus/aarch64/a64fx.S b/lib/cpus/aarch64/a64fx.S index 54c20c32b..4893a44d7 100644 --- a/lib/cpus/aarch64/a64fx.S +++ b/lib/cpus/aarch64/a64fx.S @@ -16,15 +16,6 @@ endfunc a64fx_core_pwr_dwn func a64fx_cluster_pwr_dwn endfunc a64fx_cluster_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for A64FX. Must follow AAPCS. - */ -func a64fx_errata_report - ret -endfunc a64fx_errata_report -#endif - /* --------------------------------------------- * This function provides cpu specific * register information for crash reporting. diff --git a/lib/cpus/aarch64/aem_generic.S b/lib/cpus/aarch64/aem_generic.S index d47279a76..d5634cff8 100644 --- a/lib/cpus/aarch64/aem_generic.S +++ b/lib/cpus/aarch64/aem_generic.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -74,15 +74,6 @@ func aem_generic_cluster_pwr_dwn b dcsw_op_all endfunc aem_generic_cluster_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for AEM. Must follow AAPCS. - */ -func aem_generic_errata_report - ret -endfunc aem_generic_errata_report -#endif - /* --------------------------------------------- * This function provides cpu specific * register information for crash reporting. diff --git a/lib/cpus/aarch64/cortex_a35.S b/lib/cpus/aarch64/cortex_a35.S index 6ffb94407..c3d8c8dd5 100644 --- a/lib/cpus/aarch64/cortex_a35.S +++ b/lib/cpus/aarch64/cortex_a35.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -111,8 +111,6 @@ func cortex_a35_cluster_pwr_dwn b cortex_a35_disable_smp endfunc cortex_a35_cluster_pwr_dwn -errata_report_shim cortex_a35 - /* --------------------------------------------- * This function provides cortex_a35 specific * register information for crash reporting. diff --git a/lib/cpus/aarch64/cortex_a510.S b/lib/cpus/aarch64/cortex_a510.S index a59b92c15..b49d45a22 100644 --- a/lib/cpus/aarch64/cortex_a510.S +++ b/lib/cpus/aarch64/cortex_a510.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023, Arm Limited. All rights reserved. + * Copyright (c) 2023-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -204,8 +204,6 @@ func cortex_a510_core_pwr_dwn ret endfunc cortex_a510_core_pwr_dwn -errata_report_shim cortex_a510 - cpu_reset_func_start cortex_a510 /* Disable speculative loads */ msr SSBS, xzr diff --git a/lib/cpus/aarch64/cortex_a520.S b/lib/cpus/aarch64/cortex_a520.S index 74ecbf7c9..c7bb4ddae 100644 --- a/lib/cpus/aarch64/cortex_a520.S +++ b/lib/cpus/aarch64/cortex_a520.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023, Arm Limited. All rights reserved. + * Copyright (c) 2021-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -46,8 +46,6 @@ func cortex_a520_core_pwr_dwn ret endfunc cortex_a520_core_pwr_dwn -errata_report_shim cortex_a520 - cpu_reset_func_start cortex_a520 /* Disable speculative loads */ msr SSBS, xzr diff --git a/lib/cpus/aarch64/cortex_a53.S b/lib/cpus/aarch64/cortex_a53.S index e6fb08a4e..4a5b31814 100644 --- a/lib/cpus/aarch64/cortex_a53.S +++ b/lib/cpus/aarch64/cortex_a53.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -199,8 +199,6 @@ func cortex_a53_cluster_pwr_dwn b cortex_a53_disable_smp endfunc cortex_a53_cluster_pwr_dwn -errata_report_shim cortex_a53 - /* --------------------------------------------- * This function provides cortex_a53 specific * register information for crash reporting. diff --git a/lib/cpus/aarch64/cortex_a55.S b/lib/cpus/aarch64/cortex_a55.S index 712b6e0a9..d5a74e96d 100644 --- a/lib/cpus/aarch64/cortex_a55.S +++ b/lib/cpus/aarch64/cortex_a55.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -116,8 +116,6 @@ add_erratum_entry cortex_a55, ERRATUM(1530923), ERRATA_A55_1530923, NO_APPLY_AT_ cpu_reset_func_start cortex_a55 cpu_reset_func_end cortex_a55 -errata_report_shim cortex_a55 - /* --------------------------------------------- * HW will do the cache maintenance while powering down * --------------------------------------------- diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S index 8fafacab4..374cc5d7f 100644 --- a/lib/cpus/aarch64/cortex_a57.S +++ b/lib/cpus/aarch64/cortex_a57.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -284,8 +284,6 @@ func cortex_a57_cluster_pwr_dwn b cortex_a57_disable_ext_debug endfunc cortex_a57_cluster_pwr_dwn -errata_report_shim cortex_a57 - /* --------------------------------------------- * This function provides cortex_a57 specific * register information for crash reporting. diff --git a/lib/cpus/aarch64/cortex_a65.S b/lib/cpus/aarch64/cortex_a65.S index 666324c1e..3023ecbe5 100644 --- a/lib/cpus/aarch64/cortex_a65.S +++ b/lib/cpus/aarch64/cortex_a65.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Arm Limited. All rights reserved. + * Copyright (c) 2019-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -45,26 +45,6 @@ func cortex_a65_cpu_pwr_dwn ret endfunc cortex_a65_cpu_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for Cortex-A65. Must follow AAPCS. - */ -func cortex_a65_errata_report - stp x8, x30, [sp, #-16]! - - bl cpu_get_rev_var - mov x8, x0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata ERRATA_DSU_936184, cortex_a65, dsu_936184 - - ldp x8, x30, [sp], #16 - ret -endfunc cortex_a65_errata_report -#endif .section .rodata.cortex_a65_regs, "aS" cortex_a65_regs: /* The ascii list of register names to be reported */ diff --git a/lib/cpus/aarch64/cortex_a65ae.S b/lib/cpus/aarch64/cortex_a65ae.S index 85d1894e0..1cbb06aff 100644 --- a/lib/cpus/aarch64/cortex_a65ae.S +++ b/lib/cpus/aarch64/cortex_a65ae.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2023, Arm Limited. All rights reserved. + * Copyright (c) 2019-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -41,8 +41,6 @@ func cortex_a65ae_cpu_pwr_dwn ret endfunc cortex_a65ae_cpu_pwr_dwn -errata_report_shim cortex_a65ae - .section .rodata.cortex_a65ae_regs, "aS" cortex_a65ae_regs: /* The ascii list of register names to be reported */ .asciz "cpuectlr_el1", "" diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S index b99fbb3c1..4c33dda9f 100644 --- a/lib/cpus/aarch64/cortex_a710.S +++ b/lib/cpus/aarch64/cortex_a710.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023, Arm Limited. All rights reserved. + * Copyright (c) 2021-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -229,8 +229,6 @@ func cortex_a710_core_pwr_dwn ret endfunc cortex_a710_core_pwr_dwn -errata_report_shim cortex_a710 - cpu_reset_func_start cortex_a710 /* Disable speculative loads */ msr SSBS, xzr diff --git a/lib/cpus/aarch64/cortex_a715.S b/lib/cpus/aarch64/cortex_a715.S index 16be161eb..8c9988da0 100644 --- a/lib/cpus/aarch64/cortex_a715.S +++ b/lib/cpus/aarch64/cortex_a715.S @@ -148,8 +148,6 @@ func cortex_a715_core_pwr_dwn ret endfunc cortex_a715_core_pwr_dwn -errata_report_shim cortex_a715 - /* --------------------------------------------- * This function provides Cortex-A715 specific * register information for crash reporting. diff --git a/lib/cpus/aarch64/cortex_a72.S b/lib/cpus/aarch64/cortex_a72.S index 997f261b7..c300ea7cf 100644 --- a/lib/cpus/aarch64/cortex_a72.S +++ b/lib/cpus/aarch64/cortex_a72.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -271,8 +271,6 @@ func cortex_a72_cluster_pwr_dwn b cortex_a72_disable_ext_debug endfunc cortex_a72_cluster_pwr_dwn -errata_report_shim cortex_a72 - /* --------------------------------------------- * This function provides cortex_a72 specific * register information for crash reporting. diff --git a/lib/cpus/aarch64/cortex_a720.S b/lib/cpus/aarch64/cortex_a720.S index 53a1b7897..891b62a79 100644 --- a/lib/cpus/aarch64/cortex_a720.S +++ b/lib/cpus/aarch64/cortex_a720.S @@ -80,8 +80,6 @@ func cortex_a720_core_pwr_dwn ret endfunc cortex_a720_core_pwr_dwn -errata_report_shim cortex_a720 - /* --------------------------------------------- * This function provides Cortex A720-specific * register information for crash reporting. diff --git a/lib/cpus/aarch64/cortex_a725.S b/lib/cpus/aarch64/cortex_a725.S index c08945fd1..af98d1453 100644 --- a/lib/cpus/aarch64/cortex_a725.S +++ b/lib/cpus/aarch64/cortex_a725.S @@ -40,8 +40,6 @@ func cortex_a725_core_pwr_dwn ret endfunc cortex_a725_core_pwr_dwn -errata_report_shim cortex_a725 - /* --------------------------------------------- * This function provides Cortex-A725 specific * register information for crash reporting. diff --git a/lib/cpus/aarch64/cortex_a73.S b/lib/cpus/aarch64/cortex_a73.S index 3a6b92263..2130ceb1f 100644 --- a/lib/cpus/aarch64/cortex_a73.S +++ b/lib/cpus/aarch64/cortex_a73.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -178,9 +178,6 @@ func cortex_a73_cluster_pwr_dwn b cortex_a73_disable_smp endfunc cortex_a73_cluster_pwr_dwn - -errata_report_shim cortex_a73 - /* --------------------------------------------- * This function provides cortex_a73 specific * register information for crash reporting. diff --git a/lib/cpus/aarch64/cortex_a75.S b/lib/cpus/aarch64/cortex_a75.S index c90be6794..911530391 100644 --- a/lib/cpus/aarch64/cortex_a75.S +++ b/lib/cpus/aarch64/cortex_a75.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -146,8 +146,6 @@ func cortex_a75_core_pwr_dwn ret endfunc cortex_a75_core_pwr_dwn -errata_report_shim cortex_a75 - /* --------------------------------------------- * This function provides cortex_a75 specific * register information for crash reporting. diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S index 8b3d7300e..97e036e09 100644 --- a/lib/cpus/aarch64/cortex_a76.S +++ b/lib/cpus/aarch64/cortex_a76.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -511,8 +511,6 @@ func cortex_a76_core_pwr_dwn ret endfunc cortex_a76_core_pwr_dwn -errata_report_shim cortex_a76 - /* --------------------------------------------- * This function provides cortex_a76 specific * register information for crash reporting. diff --git a/lib/cpus/aarch64/cortex_a76ae.S b/lib/cpus/aarch64/cortex_a76ae.S index 08a6ef912..2fe3dbcf7 100644 --- a/lib/cpus/aarch64/cortex_a76ae.S +++ b/lib/cpus/aarch64/cortex_a76ae.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2023, Arm Limited. All rights reserved. + * Copyright (c) 2019-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -41,8 +41,6 @@ workaround_reset_end cortex_a76ae, CVE(2022, 23960) cpu_reset_func_start cortex_a76ae cpu_reset_func_end cortex_a76ae -errata_report_shim cortex_a76ae - /* ---------------------------------------------------- * HW will do the cache maintenance while powering down * ---------------------------------------------------- diff --git a/lib/cpus/aarch64/cortex_a77.S b/lib/cpus/aarch64/cortex_a77.S index 86c256158..d1fc41af6 100644 --- a/lib/cpus/aarch64/cortex_a77.S +++ b/lib/cpus/aarch64/cortex_a77.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -167,7 +167,6 @@ func cortex_a77_core_pwr_dwn ret endfunc cortex_a77_core_pwr_dwn -errata_report_shim cortex_a77 /* --------------------------------------------- * This function provides Cortex-A77 specific * register information for crash reporting. diff --git a/lib/cpus/aarch64/cortex_a78.S b/lib/cpus/aarch64/cortex_a78.S index b5c24e143..5a63e786f 100644 --- a/lib/cpus/aarch64/cortex_a78.S +++ b/lib/cpus/aarch64/cortex_a78.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2023, Arm Limited. All rights reserved. + * Copyright (c) 2019-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -198,8 +198,6 @@ func cortex_a78_core_pwr_dwn ret endfunc cortex_a78_core_pwr_dwn -errata_report_shim cortex_a78 - /* --------------------------------------------- * This function provides cortex_a78 specific * register information for crash reporting. diff --git a/lib/cpus/aarch64/cortex_a78_ae.S b/lib/cpus/aarch64/cortex_a78_ae.S index d3a3e5d88..bc10186ff 100644 --- a/lib/cpus/aarch64/cortex_a78_ae.S +++ b/lib/cpus/aarch64/cortex_a78_ae.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2023, Arm Limited. All rights reserved. + * Copyright (c) 2019-2024, Arm Limited. All rights reserved. * Copyright (c) 2021-2023, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -128,8 +128,6 @@ func cortex_a78_ae_core_pwr_dwn ret endfunc cortex_a78_ae_core_pwr_dwn -errata_report_shim cortex_a78_ae - /* ------------------------------------------------------- * This function provides cortex_a78_ae specific * register information for crash reporting. diff --git a/lib/cpus/aarch64/cortex_a78c.S b/lib/cpus/aarch64/cortex_a78c.S index 0dc34f7ac..97d574345 100644 --- a/lib/cpus/aarch64/cortex_a78c.S +++ b/lib/cpus/aarch64/cortex_a78c.S @@ -121,8 +121,6 @@ workaround_reset_end cortex_a78c, CVE(2022, 23960) cpu_reset_func_start cortex_a78c cpu_reset_func_end cortex_a78c -errata_report_shim cortex_a78c - /* ---------------------------------------------------- * HW will do the cache maintenance while powering down * ---------------------------------------------------- diff --git a/lib/cpus/aarch64/cortex_gelas.S b/lib/cpus/aarch64/cortex_gelas.S index 887001900..891e9a653 100644 --- a/lib/cpus/aarch64/cortex_gelas.S +++ b/lib/cpus/aarch64/cortex_gelas.S @@ -58,8 +58,6 @@ func cortex_gelas_core_pwr_dwn ret endfunc cortex_gelas_core_pwr_dwn -errata_report_shim cortex_gelas - /* --------------------------------------------- * This function provides Gelas specific * register information for crash reporting. diff --git a/lib/cpus/aarch64/cortex_x1.S b/lib/cpus/aarch64/cortex_x1.S index 42634f1a7..ca6cac994 100644 --- a/lib/cpus/aarch64/cortex_x1.S +++ b/lib/cpus/aarch64/cortex_x1.S @@ -66,8 +66,6 @@ func cortex_x1_core_pwr_dwn ret endfunc cortex_x1_core_pwr_dwn -errata_report_shim cortex_x1 - /* --------------------------------------------- * This function provides Cortex X1 specific * register information for crash reporting. diff --git a/lib/cpus/aarch64/cortex_x2.S b/lib/cpus/aarch64/cortex_x2.S index d018182cc..ab0b19d9d 100644 --- a/lib/cpus/aarch64/cortex_x2.S +++ b/lib/cpus/aarch64/cortex_x2.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023, Arm Limited. All rights reserved. + * Copyright (c) 2021-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -182,8 +182,6 @@ func cortex_x2_core_pwr_dwn ret endfunc cortex_x2_core_pwr_dwn -errata_report_shim cortex_x2 - cpu_reset_func_start cortex_x2 /* Disable speculative loads */ msr SSBS, xzr diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S index 49e9ad1d3..248f10703 100644 --- a/lib/cpus/aarch64/cortex_x3.S +++ b/lib/cpus/aarch64/cortex_x3.S @@ -125,8 +125,6 @@ func cortex_x3_core_pwr_dwn ret endfunc cortex_x3_core_pwr_dwn -errata_report_shim cortex_x3 - /* --------------------------------------------- * This function provides Cortex-X3- * specific register information for crash diff --git a/lib/cpus/aarch64/cortex_x4.S b/lib/cpus/aarch64/cortex_x4.S index 20f1ae18d..04719dfa3 100644 --- a/lib/cpus/aarch64/cortex_x4.S +++ b/lib/cpus/aarch64/cortex_x4.S @@ -73,8 +73,6 @@ func cortex_x4_core_pwr_dwn ret endfunc cortex_x4_core_pwr_dwn -errata_report_shim cortex_x4 - /* --------------------------------------------- * This function provides Cortex X4-specific * register information for crash reporting. diff --git a/lib/cpus/aarch64/cortex_x925.S b/lib/cpus/aarch64/cortex_x925.S index 36b442e42..8109ffba2 100644 --- a/lib/cpus/aarch64/cortex_x925.S +++ b/lib/cpus/aarch64/cortex_x925.S @@ -40,8 +40,6 @@ func cortex_x925_core_pwr_dwn ret endfunc cortex_x925_core_pwr_dwn -errata_report_shim cortex_x925 - /* --------------------------------------------- * This function provides Cortex-X925 specific * register information for crash reporting. diff --git a/lib/cpus/aarch64/denver.S b/lib/cpus/aarch64/denver.S index 884281d30..ca250d370 100644 --- a/lib/cpus/aarch64/denver.S +++ b/lib/cpus/aarch64/denver.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -296,8 +296,6 @@ func denver_cluster_pwr_dwn ret endfunc denver_cluster_pwr_dwn -errata_report_shim denver - /* --------------------------------------------- * This function provides Denver specific * register information for crash reporting. diff --git a/lib/cpus/aarch64/generic.S b/lib/cpus/aarch64/generic.S index ef1f048a1..5d7a857e0 100644 --- a/lib/cpus/aarch64/generic.S +++ b/lib/cpus/aarch64/generic.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Arm Limited. All rights reserved. + * Copyright (c) 2020-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -79,7 +79,6 @@ endfunc generic_cluster_pwr_dwn * Unimplemented functions. * --------------------------------------------- */ -.equ generic_errata_report, 0 .equ generic_cpu_reg_dump, 0 .equ generic_reset_func, 0 diff --git a/lib/cpus/aarch64/neoverse_e1.S b/lib/cpus/aarch64/neoverse_e1.S index 45bd8d318..4bc95d054 100644 --- a/lib/cpus/aarch64/neoverse_e1.S +++ b/lib/cpus/aarch64/neoverse_e1.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -42,8 +42,6 @@ func neoverse_e1_cpu_pwr_dwn ret endfunc neoverse_e1_cpu_pwr_dwn -errata_report_shim neoverse_e1 - .section .rodata.neoverse_e1_regs, "aS" neoverse_e1_regs: /* The ascii list of register names to be reported */ .asciz "cpuectlr_el1", "" diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S index 36a7ee75a..50e1ae38b 100644 --- a/lib/cpus/aarch64/neoverse_n1.S +++ b/lib/cpus/aarch64/neoverse_n1.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -242,8 +242,6 @@ func neoverse_n1_core_pwr_dwn ret endfunc neoverse_n1_core_pwr_dwn -errata_report_shim neoverse_n1 - /* * Handle trap of EL0 IC IVAU instructions to EL3 by executing a TLB * inner-shareable invalidation to an arbitrary address followed by a DSB. diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S index a85d95682..7d7cc4473 100644 --- a/lib/cpus/aarch64/neoverse_n2.S +++ b/lib/cpus/aarch64/neoverse_n2.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2023, Arm Limited. All rights reserved. + * Copyright (c) 2020-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -282,8 +282,6 @@ func neoverse_n2_core_pwr_dwn ret endfunc neoverse_n2_core_pwr_dwn -errata_report_shim neoverse_n2 - /* --------------------------------------------- * This function provides Neoverse N2 specific * register information for crash reporting. diff --git a/lib/cpus/aarch64/neoverse_n3.S b/lib/cpus/aarch64/neoverse_n3.S index 0b33b7ed0..d96c9d46a 100644 --- a/lib/cpus/aarch64/neoverse_n3.S +++ b/lib/cpus/aarch64/neoverse_n3.S @@ -45,8 +45,6 @@ func neoverse_n3_core_pwr_dwn ret endfunc neoverse_n3_core_pwr_dwn -errata_report_shim neoverse_n3 - /* --------------------------------------------- * This function provides Neoverse-N3 specific * register information for crash reporting. diff --git a/lib/cpus/aarch64/neoverse_v1.S b/lib/cpus/aarch64/neoverse_v1.S index c2fbb1110..89299b736 100644 --- a/lib/cpus/aarch64/neoverse_v1.S +++ b/lib/cpus/aarch64/neoverse_v1.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2023, Arm Limited. All rights reserved. + * Copyright (c) 2019-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -259,8 +259,6 @@ func neoverse_v1_core_pwr_dwn ret endfunc neoverse_v1_core_pwr_dwn -errata_report_shim neoverse_v1 - cpu_reset_func_start neoverse_v1 /* Disable speculative loads */ msr SSBS, xzr diff --git a/lib/cpus/aarch64/neoverse_v2.S b/lib/cpus/aarch64/neoverse_v2.S index 317991879..d8c32a486 100644 --- a/lib/cpus/aarch64/neoverse_v2.S +++ b/lib/cpus/aarch64/neoverse_v2.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023, Arm Limited. All rights reserved. + * Copyright (c) 2021-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -116,7 +116,6 @@ cpu_reset_func_start neoverse_v2 #endif cpu_reset_func_end neoverse_v2 -errata_report_shim neoverse_v2 /* --------------------------------------------- * This function provides Neoverse V2- * specific register information for crash diff --git a/lib/cpus/aarch64/neoverse_v3.S b/lib/cpus/aarch64/neoverse_v3.S index 67258c830..01ac38f18 100644 --- a/lib/cpus/aarch64/neoverse_v3.S +++ b/lib/cpus/aarch64/neoverse_v3.S @@ -60,8 +60,6 @@ cpu_reset_func_start neoverse_v3 msr SSBS, xzr cpu_reset_func_end neoverse_v3 -errata_report_shim neoverse_v3 - /* --------------------------------------------- * This function provides Neoverse V3 specific * register information for crash reporting. diff --git a/lib/cpus/aarch64/nevis.S b/lib/cpus/aarch64/nevis.S index 36830a9b0..0180ab7d5 100644 --- a/lib/cpus/aarch64/nevis.S +++ b/lib/cpus/aarch64/nevis.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023, Arm Limited. All rights reserved. + * Copyright (c) 2023-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -40,8 +40,6 @@ func nevis_core_pwr_dwn ret endfunc nevis_core_pwr_dwn -errata_report_shim nevis - .section .rodata.nevis_regs, "aS" nevis_regs: /* The ASCII list of register names to be reported */ .asciz "cpuectlr_el1", "" diff --git a/lib/cpus/aarch64/qemu_max.S b/lib/cpus/aarch64/qemu_max.S index 00963bc3e..fb03cf15b 100644 --- a/lib/cpus/aarch64/qemu_max.S +++ b/lib/cpus/aarch64/qemu_max.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -47,8 +47,6 @@ func qemu_max_cluster_pwr_dwn b dcsw_op_all endfunc qemu_max_cluster_pwr_dwn -errata_report_shim qemu_max - /* --------------------------------------------- * This function provides cpu specific * register information for crash reporting. diff --git a/lib/cpus/aarch64/rainier.S b/lib/cpus/aarch64/rainier.S index c770f54f3..ea687be6e 100644 --- a/lib/cpus/aarch64/rainier.S +++ b/lib/cpus/aarch64/rainier.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2023, Arm Limited. All rights reserved. + * Copyright (c) 2020-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -80,8 +80,6 @@ func rainier_core_pwr_dwn ret endfunc rainier_core_pwr_dwn -errata_report_shim rainier - /* --------------------------------------------- * This function provides Rainier specific * register information for crash reporting. diff --git a/lib/cpus/aarch64/travis.S b/lib/cpus/aarch64/travis.S index ba06f557b..e8b3860b0 100644 --- a/lib/cpus/aarch64/travis.S +++ b/lib/cpus/aarch64/travis.S @@ -54,8 +54,6 @@ func travis_core_pwr_dwn ret endfunc travis_core_pwr_dwn -errata_report_shim travis - .section .rodata.travis_regs, "aS" travis_regs: /* The ASCII list of register names to be reported */ .asciz "cpuectlr_el1", "" diff --git a/plat/qti/common/src/aarch64/qti_kryo4_gold.S b/plat/qti/common/src/aarch64/qti_kryo4_gold.S index 9bcdf5425..49b7cf014 100644 --- a/plat/qti/common/src/aarch64/qti_kryo4_gold.S +++ b/plat/qti/common/src/aarch64/qti_kryo4_gold.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -41,16 +41,6 @@ func qti_kryo4_gold_cluster_pwr_dwn ret endfunc qti_kryo4_gold_cluster_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for Kryo4 Gold. Must follow AAPCS. - */ -func qti_kryo4_gold_errata_report - /* TODO : Need to add support. Required only for debug bl31 image.*/ - ret -endfunc qti_kryo4_gold_errata_report -#endif - /* --------------------------------------------- * This function provides kryo4_gold specific * register information for crash reporting. diff --git a/plat/qti/common/src/aarch64/qti_kryo4_silver.S b/plat/qti/common/src/aarch64/qti_kryo4_silver.S index 36374b739..4a98912df 100644 --- a/plat/qti/common/src/aarch64/qti_kryo4_silver.S +++ b/plat/qti/common/src/aarch64/qti_kryo4_silver.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -35,17 +35,6 @@ func qti_kryo4_silver_cluster_pwr_dwn ret endfunc qti_kryo4_silver_cluster_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for Kryo4 Silver. Must follow AAPCS. - */ -func qti_kryo4_silver_errata_report - /* TODO : Need to add support. Required only for debug bl31 image.*/ - ret -endfunc qti_kryo4_silver_errata_report -#endif - - /* --------------------------------------------- * This function provides kryo4_silver specific * register information for crash reporting. diff --git a/plat/qti/common/src/aarch64/qti_kryo6_gold.S b/plat/qti/common/src/aarch64/qti_kryo6_gold.S index 577e7ff60..5f9463f6f 100644 --- a/plat/qti/common/src/aarch64/qti_kryo6_gold.S +++ b/plat/qti/common/src/aarch64/qti_kryo6_gold.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -41,16 +41,6 @@ func qti_kryo6_gold_cluster_pwr_dwn ret endfunc qti_kryo6_gold_cluster_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for Kryo4 Gold. Must follow AAPCS. - */ -func qti_kryo6_gold_errata_report - /* TODO : Need to add support. Required only for debug bl31 image.*/ - ret -endfunc qti_kryo6_gold_errata_report -#endif - /* --------------------------------------------- * This function provides kryo4_gold specific * register information for crash reporting. diff --git a/plat/qti/common/src/aarch64/qti_kryo6_silver.S b/plat/qti/common/src/aarch64/qti_kryo6_silver.S index 6ad0bcae1..4a54a64cc 100644 --- a/plat/qti/common/src/aarch64/qti_kryo6_silver.S +++ b/plat/qti/common/src/aarch64/qti_kryo6_silver.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -35,17 +35,6 @@ func qti_kryo6_silver_cluster_pwr_dwn ret endfunc qti_kryo6_silver_cluster_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for Kryo4 Silver. Must follow AAPCS. - */ -func qti_kryo6_silver_errata_report - /* TODO : Need to add support. Required only for debug bl31 image.*/ - ret -endfunc qti_kryo6_silver_errata_report -#endif - - /* --------------------------------------------- * This function provides kryo4_silver specific * register information for crash reporting.