From 3fabca724a724266f41a210d377d79072b36e140 Mon Sep 17 00:00:00 2001 From: Harrison Mutai Date: Tue, 18 Feb 2025 14:26:08 +0000 Subject: [PATCH] feat(bl32): enable r3 usage for boot args `r3` is used to pass the base address of the transfer list. Make sure we update the context structure with this register value so it is populated with this information prior to executing the next stage. Change-Id: Ie1eedbd2eb68b592df30779625691e8975d987bf Signed-off-by: Harrison Mutai --- bl32/sp_min/sp_min_main.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/bl32/sp_min/sp_min_main.c b/bl32/sp_min/sp_min_main.c index a85b35515..9add23920 100644 --- a/bl32/sp_min/sp_min_main.c +++ b/bl32/sp_min/sp_min_main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -113,6 +113,7 @@ static void copy_cpu_ctx_to_smc_stx(const regs_t *cpu_reg_ctx, next_smc_ctx->r0 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R0); next_smc_ctx->r1 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R1); next_smc_ctx->r2 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R2); + next_smc_ctx->r3 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R3); next_smc_ctx->lr_mon = read_ctx_reg(cpu_reg_ctx, CTX_LR); next_smc_ctx->spsr_mon = read_ctx_reg(cpu_reg_ctx, CTX_SPSR); next_smc_ctx->scr = read_ctx_reg(cpu_reg_ctx, CTX_SCR);