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fix(cpus): workaround for Cortex-X3 erratum 2302506

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Cortex-X3 erratum 2302506 is a cat B erratum that applies to
revisions r0p0-r1p1 and is fixed in r1p2. The workaround is to
set bit[0] of CPUACTLR2 which will force PLDW/PFRM ST to behave
like PLD/PRFM LD and not cause invalidation to other PE caches.

There might be a small performance degradation to this workaround
for certain workloads that share data.

SDEN can be found here:
https://developer.arm.com/documentation/2055130/latest

Change-Id: I048b830867915b88afa36582c6da05734a56d22a
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
This commit is contained in:
Bipin Ravi 2023-12-20 14:32:02 -06:00
parent 23d6774ab5
commit 3f9df2c6ad
4 changed files with 25 additions and 10 deletions
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6
docs/design/cpu-specific-build-macros.rst
View file

@ -771,6 +771,10 @@ For Cortex-X3, the following errata build flags are defined :
CPU. This needs to be enabled only for revisions r0p0, r1p0, r1p1 and r1p2 of CPU. This needs to be enabled only for revisions r0p0, r1p0, r1p1 and r1p2 of
the CPU and is still open. the CPU and is still open.
- ``ERRATA_X3_2302506``: This applies errata 2302506 workaround to the Cortex-X3
CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1, it is
fixed in r1p2.
- ``ERRATA_X3_2313909``: This applies errata 2313909 workaround to - ``ERRATA_X3_2313909``: This applies errata 2313909 workaround to
Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0
of the CPU, it is fixed in r1p1. of the CPU, it is fixed in r1p1.
@ -946,7 +950,7 @@ GIC Errata Workarounds
-------------- --------------
*Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.* *Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.*
.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715 .. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715
.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639 .. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639

8
lib/cpus/aarch64/cortex_x3.S
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2021-2023, Arm Limited. All rights reserved. * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -33,6 +33,12 @@ workaround_reset_end cortex_x3, ERRATUM(2070301)
check_erratum_ls cortex_x3, ERRATUM(2070301), CPU_REV(1, 2) check_erratum_ls cortex_x3, ERRATUM(2070301), CPU_REV(1, 2)
workaround_runtime_start cortex_x3, ERRATUM(2302506), ERRATA_X3_2302506
sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, BIT(0)
workaround_runtime_end cortex_x3, ERRATUM(2302506), NO_ISB
check_erratum_ls cortex_x3, ERRATUM(2302506), CPU_REV(1, 1)
workaround_runtime_start cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909 workaround_runtime_start cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909
sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, CORTEX_X3_CPUACTLR2_EL1_BIT_36 sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, CORTEX_X3_CPUACTLR2_EL1_BIT_36
workaround_runtime_end cortex_x3, ERRATUM(2313909), NO_ISB workaround_runtime_end cortex_x3, ERRATUM(2313909), NO_ISB

6
lib/cpus/cpu-ops.mk
View file

@ -1,5 +1,5 @@
# #
# Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved. # Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.
# Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved. # Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved.
# #
# SPDX-License-Identifier: BSD-3-Clause # SPDX-License-Identifier: BSD-3-Clause
@ -774,6 +774,10 @@ CPU_FLAG_LIST += ERRATA_X2_2778471
# still open. # still open.
CPU_FLAG_LIST += ERRATA_X3_2070301 CPU_FLAG_LIST += ERRATA_X3_2070301
# Flag to apply erratum 2302506 workaround during reset. This erratum applies
# to revisions r0p0, r1p0 and r1p1 of the Cortex-X3 cpu, it is fixed in r1p2.
CPU_FLAG_LIST += ERRATA_X3_2302506
# Flag to apply erratum 2313909 workaround on powerdown. This erratum applies # Flag to apply erratum 2313909 workaround on powerdown. This erratum applies
# to revisions r0p0 and r1p0 of the Cortex-X3 cpu, it is fixed in r1p1. # to revisions r0p0 and r1p0 of the Cortex-X3 cpu, it is fixed in r1p1.
CPU_FLAG_LIST += ERRATA_X3_2313909 CPU_FLAG_LIST += ERRATA_X3_2313909

15
services/std_svc/errata_abi/errata_abi_main.c
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2023, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -446,12 +446,13 @@ struct em_cpu_list cpu_list[] = {
.cpu_partnumber = CORTEX_X3_MIDR, .cpu_partnumber = CORTEX_X3_MIDR,
.cpu_errata_list = { .cpu_errata_list = {
[0] = {2070301, 0x00, 0x12, ERRATA_X3_2070301}, [0] = {2070301, 0x00, 0x12, ERRATA_X3_2070301},
[1] = {2313909, 0x00, 0x10, ERRATA_X3_2313909}, [1] = {2302506, 0x00, 0x11, ERRATA_X3_2302506},
[2] = {2615812, 0x00, 0x11, ERRATA_X3_2615812}, [2] = {2313909, 0x00, 0x10, ERRATA_X3_2313909},
[3] = {2742421, 0x00, 0x11, ERRATA_X3_2742421}, [3] = {2615812, 0x00, 0x11, ERRATA_X3_2615812},
[4] = {2743088, 0x00, 0x11, ERRATA_X3_2743088}, [4] = {2742421, 0x00, 0x11, ERRATA_X3_2742421},
[5] = {2779509, 0x00, 0x11, ERRATA_X3_2779509}, [5] = {2743088, 0x00, 0x11, ERRATA_X3_2743088},
[6 ... ERRATA_LIST_END] = UNDEF_ERRATA, [6] = {2779509, 0x00, 0x11, ERRATA_X3_2779509},
[7 ... ERRATA_LIST_END] = UNDEF_ERRATA,
} }
}, },
#endif /* CORTEX_X3_H_INC */ #endif /* CORTEX_X3_H_INC */