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https://github.com/ARM-software/arm-trusted-firmware.git
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Merge "runtime_exceptions: Update AT speculative workaround" into integration
This commit is contained in:
Alexei Fedorov
TrustedFirmware Code Review
commit
3ee8e4d8de
3 changed files with 100 additions and 0 deletions
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@ -12,6 +12,7 @@
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#include <bl31/interrupt_mgmt.h>
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#include <common/runtime_svc.h>
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#include <context.h>
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#include <el3_common_macros.S>
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#include <lib/el3_runtime/cpu_data.h>
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#include <lib/smccc.h>
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@ -285,21 +286,25 @@ vector_entry sync_exception_aarch64
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* to a valid cpu context where the general purpose and system register
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* state can be saved.
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*/
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apply_at_speculative_wa
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check_and_unmask_ea
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handle_sync_exception
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end_vector_entry sync_exception_aarch64
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vector_entry irq_aarch64
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apply_at_speculative_wa
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check_and_unmask_ea
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handle_interrupt_exception irq_aarch64
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end_vector_entry irq_aarch64
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vector_entry fiq_aarch64
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apply_at_speculative_wa
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check_and_unmask_ea
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handle_interrupt_exception fiq_aarch64
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end_vector_entry fiq_aarch64
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vector_entry serror_aarch64
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apply_at_speculative_wa
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msr daifclr, #DAIF_ABT_BIT
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b enter_lower_el_async_ea
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end_vector_entry serror_aarch64
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@ -315,21 +320,25 @@ vector_entry sync_exception_aarch32
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* to a valid cpu context where the general purpose and system register
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* state can be saved.
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*/
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apply_at_speculative_wa
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check_and_unmask_ea
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handle_sync_exception
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end_vector_entry sync_exception_aarch32
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vector_entry irq_aarch32
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apply_at_speculative_wa
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check_and_unmask_ea
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handle_interrupt_exception irq_aarch32
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end_vector_entry irq_aarch32
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vector_entry fiq_aarch32
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apply_at_speculative_wa
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check_and_unmask_ea
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handle_interrupt_exception fiq_aarch32
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end_vector_entry fiq_aarch32
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vector_entry serror_aarch32
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apply_at_speculative_wa
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msr daifclr, #DAIF_ABT_BIT
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b enter_lower_el_async_ea
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end_vector_entry serror_aarch32
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@ -455,6 +464,8 @@ smc_unknown:
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b el3_exit
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smc_prohibited:
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restore_ptw_el1_sys_regs
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ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
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ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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mov x0, #SMC_UNK
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exception_return
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@ -9,6 +9,7 @@
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#include <arch.h>
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#include <asm_macros.S>
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#include <context.h>
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#include <lib/xlat_tables/xlat_tables_defs.h>
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/*
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@ -443,4 +444,42 @@
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#endif
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.endm
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.macro apply_at_speculative_wa
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#if ERRATA_SPECULATIVE_AT
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/*
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* Explicitly save x30 so as to free up a register and to enable
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* branching and also, save x29 which will be used in the called
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* function
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*/
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stp x29, x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
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bl save_and_update_ptw_el1_sys_regs
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ldp x29, x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
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#endif
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.endm
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.macro restore_ptw_el1_sys_regs
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#if ERRATA_SPECULATIVE_AT
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/* -----------------------------------------------------------
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* In case of ERRATA_SPECULATIVE_AT, must follow below order
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* to ensure that page table walk is not enabled until
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* restoration of all EL1 system registers. TCR_EL1 register
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* should be updated at the end which restores previous page
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* table walk setting of stage1 i.e.(TCR_EL1.EPDx) bits. ISB
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* ensures that CPU does below steps in order.
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*
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* 1. Ensure all other system registers are written before
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* updating SCTLR_EL1 using ISB.
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* 2. Restore SCTLR_EL1 register.
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* 3. Ensure SCTLR_EL1 written successfully using ISB.
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* 4. Restore TCR_EL1 register.
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* -----------------------------------------------------------
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*/
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isb
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ldp x28, x29, [sp, #CTX_EL1_SYSREGS_OFFSET + CTX_SCTLR_EL1]
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msr sctlr_el1, x28
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isb
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msr tcr_el1, x29
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#endif
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.endm
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#endif /* EL3_COMMON_MACROS_S */
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@ -8,6 +8,7 @@
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <context.h>
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#include <el3_common_macros.S>
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#if CTX_INCLUDE_EL2_REGS
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.global el2_sysregs_context_save
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@ -22,6 +23,7 @@
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#endif
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.global save_gp_pmcr_pauth_regs
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.global restore_gp_pmcr_pauth_regs
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.global save_and_update_ptw_el1_sys_regs
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.global el3_exit
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#if CTX_INCLUDE_EL2_REGS
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@ -420,9 +422,11 @@ func el1_sysregs_context_save
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mrs x10, elr_el1
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stp x9, x10, [x0, #CTX_SPSR_EL1]
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#if !ERRATA_SPECULATIVE_AT
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mrs x15, sctlr_el1
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mrs x16, tcr_el1
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stp x15, x16, [x0, #CTX_SCTLR_EL1]
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#endif
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mrs x17, cpacr_el1
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mrs x9, csselr_el1
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@ -517,9 +521,11 @@ func el1_sysregs_context_restore
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msr spsr_el1, x9
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msr elr_el1, x10
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#if !ERRATA_SPECULATIVE_AT
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ldp x15, x16, [x0, #CTX_SCTLR_EL1]
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msr sctlr_el1, x15
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msr tcr_el1, x16
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#endif
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ldp x17, x9, [x0, #CTX_CPACR_EL1]
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msr cpacr_el1, x17
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@ -859,6 +865,48 @@ func restore_gp_pmcr_pauth_regs
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ret
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endfunc restore_gp_pmcr_pauth_regs
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/*
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* In case of ERRATA_SPECULATIVE_AT, save SCTLR_EL1 and TCR_EL1
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* registers and update EL1 registers to disable stage1 and stage2
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* page table walk
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*/
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func save_and_update_ptw_el1_sys_regs
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/* ----------------------------------------------------------
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* Save only sctlr_el1 and tcr_el1 registers
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* ----------------------------------------------------------
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*/
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mrs x29, sctlr_el1
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str x29, [sp, #(CTX_EL1_SYSREGS_OFFSET + CTX_SCTLR_EL1)]
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mrs x29, tcr_el1
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str x29, [sp, #(CTX_EL1_SYSREGS_OFFSET + CTX_TCR_EL1)]
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/* ------------------------------------------------------------
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* Must follow below order in order to disable page table
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* walk for lower ELs (EL1 and EL0). First step ensures that
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* page table walk is disabled for stage1 and second step
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* ensures that page table walker should use TCR_EL1.EPDx
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* bits to perform address translation. ISB ensures that CPU
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* does these 2 steps in order.
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*
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* 1. Update TCR_EL1.EPDx bits to disable page table walk by
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* stage1.
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* 2. Enable MMU bit to avoid identity mapping via stage2
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* and force TCR_EL1.EPDx to be used by the page table
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* walker.
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* ------------------------------------------------------------
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*/
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orr x29, x29, #(TCR_EPD0_BIT)
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orr x29, x29, #(TCR_EPD1_BIT)
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msr tcr_el1, x29
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isb
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mrs x29, sctlr_el1
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orr x29, x29, #SCTLR_M_BIT
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msr sctlr_el1, x29
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isb
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ret
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endfunc save_and_update_ptw_el1_sys_regs
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/* ------------------------------------------------------------------
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* This routine assumes that the SP_EL3 is pointing to a valid
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* context structure from where the gp regs and other special
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@ -903,6 +951,8 @@ func el3_exit
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blr x17
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1:
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#endif
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restore_ptw_el1_sys_regs
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/* ----------------------------------------------------------
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* Restore general purpose (including x30), PMCR_EL0 and
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* ARMv8.3-PAuth registers.
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