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drivers: synopsys: Fix synopsys MMC driver
There are some issues with synopsys MMC driver: - CMD8 should not expect data (for SD) - ACMD51 should expect data (Send SCR for SD) - dw_prepare should not dictate size to be MMC_BLOCK_SIZE, block size is now handled in the dw_prepare function - after the CMD completes, when doing dw_read, we need to invalidate cache and wait for the data transfer to complete - Need to set FIFO threshold, otherwise DMA might never get the interrupt to read or write Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
This commit is contained in:
parent
1cf55aba49
commit
3d0f30bb54
2 changed files with 29 additions and 1 deletions
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@ -243,6 +243,11 @@ static int dw_send_cmd(struct mmc_cmd *cmd)
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op = CMD_WAIT_PRVDATA_COMPLETE;
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break;
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case 8:
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if (dw_params.mmc_dev_type == MMC_IS_EMMC)
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op = CMD_DATA_TRANS_EXPECT | CMD_WAIT_PRVDATA_COMPLETE;
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else
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op = CMD_WAIT_PRVDATA_COMPLETE;
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break;
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case 17:
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case 18:
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op = CMD_DATA_TRANS_EXPECT | CMD_WAIT_PRVDATA_COMPLETE;
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@ -252,6 +257,9 @@ static int dw_send_cmd(struct mmc_cmd *cmd)
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op = CMD_WRITE | CMD_DATA_TRANS_EXPECT |
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CMD_WAIT_PRVDATA_COMPLETE;
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break;
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case 51:
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op = CMD_DATA_TRANS_EXPECT;
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break;
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default:
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op = 0;
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break;
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@ -337,7 +345,6 @@ static int dw_prepare(int lba, uintptr_t buf, size_t size)
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uintptr_t base;
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assert(((buf & DWMMC_ADDRESS_MASK) == 0) &&
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((size % MMC_BLOCK_SIZE) == 0) &&
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(dw_params.desc_size > 0) &&
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((dw_params.reg_base & MMC_BLOCK_MASK) == 0) &&
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((dw_params.desc_base & MMC_BLOCK_MASK) == 0) &&
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@ -352,6 +359,12 @@ static int dw_prepare(int lba, uintptr_t buf, size_t size)
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base = dw_params.reg_base;
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desc = (struct dw_idmac_desc *)dw_params.desc_base;
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mmio_write_32(base + DWMMC_BYTCNT, size);
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if (size < MMC_BLOCK_SIZE)
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mmio_write_32(base + DWMMC_BLKSIZ, size);
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else
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mmio_write_32(base + DWMMC_BLKSIZ, MMC_BLOCK_SIZE);
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mmio_write_32(base + DWMMC_RINTSTS, ~0);
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for (i = 0; i < desc_cnt; i++) {
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desc[i].des0 = IDMAC_DES0_OWN | IDMAC_DES0_CH | IDMAC_DES0_DIC;
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@ -375,11 +388,22 @@ static int dw_prepare(int lba, uintptr_t buf, size_t size)
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flush_dcache_range(dw_params.desc_base,
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desc_cnt * DWMMC_DMA_MAX_BUFFER_SIZE);
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return 0;
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}
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static int dw_read(int lba, uintptr_t buf, size_t size)
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{
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uint32_t data = 0;
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int timeout = TIMEOUT;
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do {
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data = mmio_read_32(dw_params.reg_base + DWMMC_RINTSTS);
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udelay(50);
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} while (!(data & INT_DTO) && timeout-- > 0);
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inv_dcache_range(buf, size);
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return 0;
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}
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@ -401,6 +425,9 @@ void dw_mmc_init(dw_mmc_params_t *params, struct mmc_device_info *info)
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(params->bus_width == MMC_BUS_WIDTH_8)));
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memcpy(&dw_params, params, sizeof(dw_mmc_params_t));
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mmio_write_32(dw_params.reg_base + DWMMC_FIFOTH, 0x103ff);
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mmc_init(&dw_mmc_ops, params->clk_rate, params->bus_width,
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params->flags, info);
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dw_params.mmc_dev_type = info->mmc_dev_type;
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}
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@ -16,6 +16,7 @@ typedef struct dw_mmc_params {
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int clk_rate;
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int bus_width;
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unsigned int flags;
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enum mmc_device_type mmc_dev_type;
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} dw_mmc_params_t;
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void dw_mmc_init(dw_mmc_params_t *params, struct mmc_device_info *info);
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