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feat(tc): add device tree binding for TC4

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Since TC3 and TC4 share most components in the hardware design, they can
reuse the device tree binding. For this reason, this patch extracts the
common modules from tc3.dts and put into the file tc3-4-based.dtsi.

As a result, a new created tc4.dts file includes tc3-4-based.dtsi for
support DT binding for the TC4 platform.

Change-Id: Ib7497162cb131d94a722aeaa14a1a37fb0095829
Signed-off-by: Leo Yan <leo.yan@arm.com>
This commit is contained in:
Leo Yan 2024-04-30 11:27:17 +01:00
parent 8fb91783ff
commit 3cedc47b1d
3 changed files with 111 additions and 76 deletions
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84
fdts/tc3-4-base.dtsi Normal file
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@ -0,0 +1,84 @@
/*
* Copyright (c) 2020-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#define LIT_CAPACITY 239
#define MID_CAPACITY 686
#define BIG_CAPACITY 1024
#define MHU_TX_COMPAT "arm,mhuv3"
#define MHU_TX_INT_NAME ""
#define MHU_RX_COMPAT "arm,mhuv3"
#define MHU_OFFSET 0x10000
#define MHU_MBOX_CELLS 3
#define MHU_RX_INT_NUM 300
#define MHU_RX_INT_NAME "combined-mbx"
#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */
#define UARTCLK_FREQ 3750000
#if TARGET_FLAVOUR_FVP
#define DPU_ADDR 4000000000
#define DPU_IRQ 579
#elif TARGET_FLAVOUR_FPGA
#define DPU_ADDR 2cc00000
#define DPU_IRQ 69
#endif
#include "tc-base.dtsi"
/ {
cpus {
CPU2:cpu@200 {
clocks = <&scmi_dvfs 1>;
capacity-dmips-mhz = <MID_CAPACITY>;
};
CPU3:cpu@300 {
clocks = <&scmi_dvfs 1>;
capacity-dmips-mhz = <MID_CAPACITY>;
};
CPU6:cpu@600 {
clocks = <&scmi_dvfs 2>;
capacity-dmips-mhz = <BIG_CAPACITY>;
};
CPU7:cpu@700 {
clocks = <&scmi_dvfs 2>;
capacity-dmips-mhz = <BIG_CAPACITY>;
};
};
gic: interrupt-controller@GIC_CTRL_ADDR {
ppi-partitions {
ppi_partition_little: interrupt-partition-0 {
affinity = <&CPU0>, <&CPU1>;
};
ppi_partition_mid: interrupt-partition-1 {
affinity = <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>;
};
ppi_partition_big: interrupt-partition-2 {
affinity = <&CPU6>, <&CPU7>;
};
};
};
sram: sram@6000000 {
cpu_scp_scmi_p2a: scp-shmem@80 {
compatible = "arm,scmi-shmem";
reg = <0x80 0x80>;
};
};
firmware {
scmi {
mboxes = <&mbox_db_tx 0 0 0 &mbox_db_rx 0 0 0 &mbox_db_rx 0 0 1>;
shmem = <&cpu_scp_scmi_a2p &cpu_scp_scmi_p2a>;
};
};
};

77
fdts/tc3.dts
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@ -10,67 +10,22 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <platform_def.h>
#define LIT_CAPACITY 239
#define MID_CAPACITY 686
#define BIG_CAPACITY 1024
#define MHU_TX_ADDR 46040000 /* hex */
#define MHU_TX_COMPAT "arm,mhuv3"
#define MHU_TX_INT_NAME ""
#define MHU_RX_ADDR 46140000 /* hex */
#define MHU_RX_COMPAT "arm,mhuv3"
#define MHU_OFFSET 0x10000
#define MHU_MBOX_CELLS 3
#define MHU_RX_INT_NUM 300
#define MHU_RX_INT_NAME "combined-mbx"
#define LIT_CPU_PMU_COMPATIBLE "arm,cortex-a520-pmu"
#define MID_CPU_PMU_COMPATIBLE "arm,cortex-a725-pmu"
#define BIG_CPU_PMU_COMPATIBLE "arm,cortex-x925-pmu"
#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */
#define UARTCLK_FREQ 3750000
#if TARGET_FLAVOUR_FVP
#define DPU_ADDR 4000000000
#define DPU_IRQ 579
#elif TARGET_FLAVOUR_FPGA
#define DPU_ADDR 2cc00000
#define DPU_IRQ 69
#endif
#include "tc-common.dtsi"
#if TARGET_FLAVOUR_FVP
#include "tc-fvp.dtsi"
#else
#include "tc-fpga.dtsi"
#endif /* TARGET_FLAVOUR_FVP */
#include "tc-base.dtsi"
#include "tc3-4-base.dtsi"
/ {
cpus {
CPU2:cpu@200 {
clocks = <&scmi_dvfs 1>;
capacity-dmips-mhz = <MID_CAPACITY>;
};
CPU3:cpu@300 {
clocks = <&scmi_dvfs 1>;
capacity-dmips-mhz = <MID_CAPACITY>;
};
CPU6:cpu@600 {
clocks = <&scmi_dvfs 2>;
capacity-dmips-mhz = <BIG_CAPACITY>;
};
CPU7:cpu@700 {
clocks = <&scmi_dvfs 2>;
capacity-dmips-mhz = <BIG_CAPACITY>;
};
};
cs-pmu@0 {
compatible = "arm,coresight-pmu";
reg = <0x0 MCN_PMU_ADDR(0) 0x0 0xffc>;
@ -109,36 +64,6 @@
reg = <0x0 0x4f000000 0x0 0x4000000>;
};
sram: sram@6000000 {
cpu_scp_scmi_p2a: scp-shmem@80 {
compatible = "arm,scmi-shmem";
reg = <0x80 0x80>;
};
};
firmware {
scmi {
mboxes = <&mbox_db_tx 0 0 0 &mbox_db_rx 0 0 0 &mbox_db_rx 0 0 1>;
shmem = <&cpu_scp_scmi_a2p &cpu_scp_scmi_p2a>;
};
};
gic: interrupt-controller@GIC_CTRL_ADDR {
ppi-partitions {
ppi_partition_little: interrupt-partition-0 {
affinity = <&CPU0>, <&CPU1>;
};
ppi_partition_mid: interrupt-partition-1 {
affinity = <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>;
};
ppi_partition_big: interrupt-partition-2 {
affinity = <&CPU6>, <&CPU7>;
};
};
};
#if TARGET_FLAVOUR_FVP
smmu_700: iommu@3f000000 {
status = "okay";

26
fdts/tc4.dts Normal file
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@ -0,0 +1,26 @@
/*
* Copyright (c) 2020-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <platform_def.h>
#define MHU_TX_ADDR 46240000 /* hex */
#define MHU_RX_ADDR 46250000 /* hex */
#define LIT_CPU_PMU_COMPATIBLE "arm,armv8-pmuv3"
#define MID_CPU_PMU_COMPATIBLE "arm,armv8-pmuv3"
#define BIG_CPU_PMU_COMPATIBLE "arm,armv8-pmuv3"
#include "tc-common.dtsi"
#if TARGET_FLAVOUR_FVP
#include "tc-fvp.dtsi"
#else
#include "tc-fpga.dtsi"
#endif /* TARGET_FLAVOUR_FVP */
#include "tc3-4-base.dtsi"