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fix(errata): workaround for Cortex-A78 erratum 2395406

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Cortex-A78 erratum 2395406 is a cat B erratum that applies to revisions
r0p0 - r1p2 and is still open. The workaround is to set bit[40] of
CPUACTLR2 which will disable folding of demand requests into older
prefetches with L2 miss requests outstanding.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1401784

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: If06f988f05f925c2a4bed3e6a9414b6acdfec894
This commit is contained in:
John Powell 2022-05-03 15:52:11 -05:00
parent 5d796b3a25
commit 3b577ed53d
3 changed files with 46 additions and 0 deletions
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4
docs/design/cpu-specific-build-macros.rst
View file

@ -300,6 +300,10 @@ For Cortex-A78, the following errata build flags are defined :
CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and
it is still open.
- ``ERRATA_A78_2395406``: This applies errata 2395406 workaround to Cortex-A78
CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and
it is still open.
For Cortex-A78 AE, the following errata build flags are defined :
- ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to

34
lib/cpus/aarch64/cortex_a78.S
View file

@ -295,6 +295,34 @@ func check_errata_2376745
b cpu_rev_var_ls
endfunc check_errata_2376745
/* --------------------------------------------------
* Errata Workaround for Cortex A78 Errata 2395406.
* This applies to revisions r0p0, r1p0, r1p1, and r1p2.
* It is still open.
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x1, x17
* --------------------------------------------------
*/
func errata_a78_2395406_wa
/* Check revision. */
mov x17, x30
bl check_errata_2395406
cbz x0, 1f
/* Apply the workaround. */
mrs x1, CORTEX_A78_ACTLR2_EL1
orr x1, x1, #BIT(40)
msr CORTEX_A78_ACTLR2_EL1, x1
1:
ret x17
endfunc errata_a78_2395406_wa
func check_errata_2395406
/* Applies to r0p0, r0p1, r1p1, and r1p2 */
mov x1, #CPU_REV(1, 2)
b cpu_rev_var_ls
endfunc check_errata_2395406
func check_errata_cve_2022_23960
#if WORKAROUND_CVE_2022_23960
mov x0, #ERRATA_APPLIES
@ -353,6 +381,11 @@ func cortex_a78_reset_func
bl errata_a78_2376745_wa
#endif
#if ERRATA_A78_2395406
mov x0, x18
bl errata_a78_2395406_wa
#endif
#if ENABLE_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
mrs x0, actlr_el3
@ -424,6 +457,7 @@ func cortex_a78_errata_report
report_errata ERRATA_A78_2132060, cortex_a78, 2132060
report_errata ERRATA_A78_2242635, cortex_a78, 2242635
report_errata ERRATA_A78_2376745, cortex_a78, 2376745
report_errata ERRATA_A78_2395406, cortex_a78, 2395406
report_errata WORKAROUND_CVE_2022_23960, cortex_a78, cve_2022_23960
ldp x8, x30, [sp], #16

8
lib/cpus/cpu-ops.mk
View file

@ -337,6 +337,10 @@ ERRATA_A78_2242635 ?=0
# to revisions r0p0, r1p0, r1p1, and r1p2 of the A78 cpu. It is still open.
ERRATA_A78_2376745 ?=0
# Flag to apply erratum 2395406 workaround during reset. This erratum applies
# to revisions r0p0, r1p0, r1p1, and r1p2 of the A78 cpu. It is still open.
ERRATA_A78_2395406 ?=0
# Flag to apply erratum 1941500 workaround during reset. This erratum applies
# to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open.
ERRATA_A78_AE_1941500 ?=0
@ -850,6 +854,10 @@ $(eval $(call add_define,ERRATA_A78_2242635))
$(eval $(call assert_boolean,ERRATA_A78_2376745))
$(eval $(call add_define,ERRATA_A78_2376745))
# Process ERRATA_A78_2395406 flag
$(eval $(call assert_boolean,ERRATA_A78_2395406))
$(eval $(call add_define,ERRATA_A78_2395406))
# Process ERRATA_A78_AE_1941500 flag
$(eval $(call assert_boolean,ERRATA_A78_AE_1941500))
$(eval $(call add_define,ERRATA_A78_AE_1941500))