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https://github.com/ARM-software/arm-trusted-firmware.git
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commit
3b39efa49d
3 changed files with 35 additions and 0 deletions
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@ -489,6 +489,15 @@ static void hikey_mmc_pll_init(void)
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reset_mmc1_clk();
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reset_mmc1_clk();
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}
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}
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static void hikey_rtc_init(void)
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{
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uint32_t data;
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data = mmio_read_32(AO_SC_PERIPH_CLKEN4);
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data |= AO_SC_PERIPH_RSTDIS4_RESET_RTC0_N;
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mmio_write_32(AO_SC_PERIPH_CLKEN4, data);
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}
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/*
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/*
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* Function which will perform any remaining platform-specific setup that can
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* Function which will perform any remaining platform-specific setup that can
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* occur after the MMU and data cache have been enabled.
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* occur after the MMU and data cache have been enabled.
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@ -505,6 +514,8 @@ void bl1_platform_setup(void)
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hikey_pmussi_init();
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hikey_pmussi_init();
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hikey_hi6553_init();
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hikey_hi6553_init();
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hikey_rtc_init();
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hikey_mmc_pll_init();
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hikey_mmc_pll_init();
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memset(¶ms, 0, sizeof(dw_mmc_params_t));
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memset(¶ms, 0, sizeof(dw_mmc_params_t));
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@ -16,6 +16,7 @@
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#include <hi6220.h>
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#include <hi6220.h>
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#include <hisi_ipc.h>
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#include <hisi_ipc.h>
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#include <hisi_pwrc.h>
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#include <hisi_pwrc.h>
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#include <mmio.h>
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#include <platform_def.h>
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#include <platform_def.h>
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#include "hikey_def.h"
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#include "hikey_def.h"
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@ -152,6 +153,20 @@ void bl31_plat_arch_setup(void)
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BL31_COHERENT_RAM_LIMIT);
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BL31_COHERENT_RAM_LIMIT);
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}
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}
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/* Initialize EDMAC controller with non-secure mode. */
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static void hikey_edma_init(void)
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{
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int i;
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uint32_t non_secure;
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non_secure = EDMAC_SEC_CTRL_INTR_SEC | EDMAC_SEC_CTRL_GLOBAL_SEC;
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mmio_write_32(EDMAC_SEC_CTRL, non_secure);
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for (i = 0; i < EDMAC_CHANNEL_NUMS; i++) {
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mmio_write_32(EDMAC_AXI_CONF(i), (1 << 6) | (1 << 18));
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}
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}
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void bl31_platform_setup(void)
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void bl31_platform_setup(void)
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{
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{
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/* Initialize the GIC driver, cpu and distributor interfaces */
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/* Initialize the GIC driver, cpu and distributor interfaces */
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@ -160,6 +175,8 @@ void bl31_platform_setup(void)
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gicv2_pcpu_distif_init();
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gicv2_pcpu_distif_init();
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gicv2_cpuif_enable();
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gicv2_cpuif_enable();
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hikey_edma_init();
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hisi_ipc_init();
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hisi_ipc_init();
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hisi_pwrc_setup();
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hisi_pwrc_setup();
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}
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}
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@ -42,6 +42,13 @@
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#define DWUSB_BASE 0xF72C0000
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#define DWUSB_BASE 0xF72C0000
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#define EDMAC_BASE 0xf7370000
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#define EDMAC_SEC_CTRL (EDMAC_BASE + 0x694)
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#define EDMAC_AXI_CONF(x) (EDMAC_BASE + 0x820 + (x << 6))
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#define EDMAC_SEC_CTRL_INTR_SEC (1 << 1)
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#define EDMAC_SEC_CTRL_GLOBAL_SEC (1 << 0)
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#define EDMAC_CHANNEL_NUMS 16
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#define PMUSSI_BASE 0xF8000000
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#define PMUSSI_BASE 0xF8000000
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#define SP804_TIMER0_BASE 0xF8008000
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#define SP804_TIMER0_BASE 0xF8008000
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