fix(errata): workaround for Neoverse-V1 erratum 2294912

Neoverse-V1 erratum 2294912 is a cat B erratum that applies to revisions
r0p0 - r1p1 and is still open. The workaround is to set bit[0] of
CPUACTLR2_EL1 to force PLDW/PFRM ST to behave like PLD/PRFM LD and not
cause invalidations to other PE caches.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1401781/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ia7afb4c42fe66b36fdf38a7d4281a0d168f68354
This commit is contained in:
Bipin Ravi 2022-06-08 16:28:46 -05:00
parent bc779e1629
commit 39eb5ddbbf
4 changed files with 47 additions and 0 deletions

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@ -414,6 +414,10 @@ For Neoverse V1, the following errata build flags are defined :
issue is present in r0p0 as well but there is no workaround for that
revision. It is still open.
- ``ERRATA_V1_2294912``: This applies errata 2294912 workaround to Neoverse-V1
CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU.
It is still open.
For Cortex-A710, the following errata build flags are defined :
- ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to

View file

@ -32,6 +32,7 @@
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
#define NEOVERSE_V1_ACTLR2_EL1 S3_0_C15_C1_1
#define NEOVERSE_V1_ACTLR2_EL1_BIT_0 ULL(1)
#define NEOVERSE_V1_ACTLR2_EL1_BIT_2 (ULL(1) << 2)
#define NEOVERSE_V1_ACTLR2_EL1_BIT_28 (ULL(1) << 28)

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@ -330,6 +330,34 @@ func check_errata_2216392
b cpu_rev_var_range
endfunc check_errata_2216392
/* -----------------------------------------------------------------
* Errata Workaround for Neoverse V1 Errata #2294912.
* This applies to revisions r0p0, r1p0, and r1p1 and is still open.
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* -----------------------------------------------------------------
*/
func errata_neoverse_v1_2294912_wa
/* Check workaround compatibility. */
mov x17, x30
bl check_errata_2294912
cbz x0, 1f
/* Set bit 0 in ACTLR2_EL1 */
mrs x1, NEOVERSE_V1_ACTLR2_EL1
orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_0
msr NEOVERSE_V1_ACTLR2_EL1, x1
isb
1:
ret x17
endfunc errata_neoverse_v1_2294912_wa
func check_errata_2294912
/* Applies to r0p0, r1p0, and r1p1 right now */
mov x1, #0x11
b cpu_rev_var_ls
endfunc check_errata_2294912
func check_errata_cve_2022_23960
#if WORKAROUND_CVE_2022_23960
mov x0, #ERRATA_APPLIES
@ -378,6 +406,7 @@ func neoverse_v1_errata_report
report_errata ERRATA_V1_2139242, neoverse_v1, 2139242
report_errata ERRATA_V1_2108267, neoverse_v1, 2108267
report_errata ERRATA_V1_2216392, neoverse_v1, 2216392
report_errata ERRATA_V1_2294912, neoverse_v1, 2294912
report_errata WORKAROUND_CVE_2022_23960, neoverse_v1, cve_2022_23960
ldp x8, x30, [sp], #16
@ -437,6 +466,11 @@ func neoverse_v1_reset_func
bl errata_neoverse_v1_2216392_wa
#endif
#if ERRATA_V1_2294912
mov x0, x18
bl errata_neoverse_v1_2294912_wa
#endif
#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
/*
* The Neoverse-V1 generic vectors are overridden to apply errata

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@ -468,6 +468,10 @@ ERRATA_V1_2108267 ?=0
# issue exists in r0p0 as well but there is no workaround for that revision.
ERRATA_V1_2216392 ?=0
# Flag to apply erratum 2294912 workaround during reset. This erratum applies
# to revisions r0p0, r1p0, and r1p1 of the Neoverse V1 cpu and is still open.
ERRATA_V1_2294912 ?=0
# Flag to apply erratum 1987031 workaround during reset. This erratum applies
# to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open.
ERRATA_A710_1987031 ?=0
@ -1003,6 +1007,10 @@ $(eval $(call add_define,ERRATA_V1_2108267))
$(eval $(call assert_boolean,ERRATA_V1_2216392))
$(eval $(call add_define,ERRATA_V1_2216392))
# Process ERRATA_V1_2294912 flag
$(eval $(call assert_boolean,ERRATA_V1_2294912))
$(eval $(call add_define,ERRATA_V1_2294912))
# Process ERRATA_A710_1987031 flag
$(eval $(call assert_boolean,ERRATA_A710_1987031))
$(eval $(call add_define,ERRATA_A710_1987031))