Disable workaround for CVE-2017-5715 on unaffected platforms

Change-Id: Ib67b841ab621ca1ace3280e44cf3e1d83052cb73
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>

plat/hisilicon/hikey/platform.mk

@@ -122,4 +122,6 @@ ERRATA_A53_836870		:=	1
 ERRATA_A53_843419		:=	1
 ERRATA_A53_855873		:=	1
 
+WORKAROUND_CVE_2017_5715	:=	0
+
 FIP_ALIGN			:=	512

plat/hisilicon/poplar/platform.mk

@@ -29,6 +29,8 @@ ERRATA_A53_835769		:= 1
 ERRATA_A53_843419		:= 1
 ENABLE_SVE_FOR_NS		:= 0
 
+WORKAROUND_CVE_2017_5715	:= 0
+
 ARM_GIC_ARCH			:= 2
 $(eval $(call add_define,ARM_GIC_ARCH))
 

plat/mediatek/mt6795/platform.mk

@@ -61,6 +61,8 @@ $(eval $(call add_define,ARM_GIC_ARCH))
 ERRATA_A53_826319	:=	1
 ERRATA_A53_836870	:=	1
 
+WORKAROUND_CVE_2017_5715	:=	0
+
 # indicate the reset vector address can be programmed
 PROGRAMMABLE_RESET_ADDRESS	:=	1
 

plat/rockchip/rk3328/platform.mk

@@ -58,3 +58,5 @@ $(eval $(call add_define,PLAT_SKIP_OPTEE_S_EL1_INT_REGISTER))
 
 # Do not enable SVE
 ENABLE_SVE_FOR_NS	:=	0
+
+WORKAROUND_CVE_2017_5715	:=	0

plat/rockchip/rk3368/platform.mk

@@ -57,3 +57,5 @@ $(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
 
 # Do not enable SVE
 ENABLE_SVE_FOR_NS	:=	0
+
+WORKAROUND_CVE_2017_5715	:=	0

plat/rpi3/platform.mk

@@ -64,6 +64,8 @@ ERRATA_A53_836870		:= 1
 ERRATA_A53_843419		:= 1
 ERRATA_A53_855873		:= 1
 
+WORKAROUND_CVE_2017_5715	:= 0
+
 # Disable the PSCI platform compatibility layer by default
 ENABLE_PLAT_COMPAT		:= 0
 

plat/xilinx/zynqmp/platform.mk

@@ -14,6 +14,8 @@ override RESET_TO_BL31 := 1
 # Do not enable SVE
 ENABLE_SVE_FOR_NS	:= 0
 
+WORKAROUND_CVE_2017_5715	:=	0
+
 ifdef ZYNQMP_ATF_MEM_BASE
     $(eval $(call add_define,ZYNQMP_ATF_MEM_BASE))