From 355ce0a43abc1559b072b9cd9905f5194a6f0b86 Mon Sep 17 00:00:00 2001 From: Sona Mathew Date: Mon, 6 Nov 2023 13:48:22 -0600 Subject: [PATCH] fix(cpus): workaround for Cortex-X3 erratum 2779509 Cortex-X3 erratum 2779509 is a Cat B erratum that applies to all revisions <= r1p1 and is fixed in r1p2. The workaround is to set chicken bit CPUACTLR3_EL1[47], this might have a small impact on power and has negligible impact on performance. SDEN documentation: https://developer.arm.com/documentation/2055130/latest Change-Id: Id92dbae6f1f313b133ffaa018fbf9c078da55d75 Signed-off-by: Sona Mathew --- docs/design/cpu-specific-build-macros.rst | 4 ++++ include/lib/cpus/aarch64/cortex_x3.h | 6 ++++++ lib/cpus/aarch64/cortex_x3.S | 7 +++++++ lib/cpus/cpu-ops.mk | 4 ++++ services/std_svc/errata_abi/errata_abi_main.c | 3 ++- 5 files changed, 23 insertions(+), 1 deletion(-) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index d03daf89f..8743b040a 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -759,6 +759,10 @@ For Cortex-X3, the following errata build flags are defined : Cortex-X3 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1. It is fixed in r1p2. +- ``ERRATA_X3_2779509``: This applies errata 2779509 workaround to Cortex-X3 + CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the + CPU. It is fixed in r1p2. + For Cortex-A510, the following errata build flags are defined : - ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to diff --git a/include/lib/cpus/aarch64/cortex_x3.h b/include/lib/cpus/aarch64/cortex_x3.h index 04548eae4..4a3ac775e 100644 --- a/include/lib/cpus/aarch64/cortex_x3.h +++ b/include/lib/cpus/aarch64/cortex_x3.h @@ -47,4 +47,10 @@ #define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_WIDTH U(4) #define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(0x9) +/******************************************************************************* + * CPU Auxiliary Control register 3 specific definitions. + ******************************************************************************/ +#define CORTEX_X3_CPUACTLR3_EL1 S3_0_C15_C1_2 +#define CORTEX_X3_CPUACTLR3_EL1_BIT_47 (ULL(1) << 47) + #endif /* CORTEX_X3_H */ diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S index 0cb3b976b..95f3d1071 100644 --- a/lib/cpus/aarch64/cortex_x3.S +++ b/lib/cpus/aarch64/cortex_x3.S @@ -57,6 +57,13 @@ workaround_reset_end cortex_x3, ERRATUM(2742421) check_erratum_ls cortex_x3, ERRATUM(2742421), CPU_REV(1, 1) +workaround_reset_start cortex_x3, ERRATUM(2779509), ERRATA_X3_2779509 + /* Set CPUACTLR3_EL1 bit 47 */ + sysreg_bit_set CORTEX_X3_CPUACTLR3_EL1, CORTEX_X3_CPUACTLR3_EL1_BIT_47 +workaround_reset_end cortex_x3, ERRATUM(2779509) + +check_erratum_ls cortex_x3, ERRATUM(2779509), CPU_REV(1, 1) + workaround_reset_start cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 #if IMAGE_BL31 override_vector_table wa_cve_vbar_cortex_x3 diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 434ee081c..283314b58 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -769,6 +769,10 @@ CPU_FLAG_LIST += ERRATA_X3_2615812 # to revisions r0p0, r1p0 and r1p1 of the Cortex-X3 cpu, it is fixed in r1p2. CPU_FLAG_LIST += ERRATA_X3_2742421 +# Flag to apply erratum 2779509 workaround on reset. This erratum applies +# to revisions r0p0, r1p0, r1p1 of the Cortex-X3 cpu, it is fixed in r1p2. +CPU_FLAG_LIST += ERRATA_X3_2779509 + # Flag to apply erratum 1922240 workaround during reset. This erratum applies # to revision r0p0 of the Cortex-A510 cpu and is fixed in r0p1. CPU_FLAG_LIST += ERRATA_A510_1922240 diff --git a/services/std_svc/errata_abi/errata_abi_main.c b/services/std_svc/errata_abi/errata_abi_main.c index 0b263e5f1..2267b2649 100644 --- a/services/std_svc/errata_abi/errata_abi_main.c +++ b/services/std_svc/errata_abi/errata_abi_main.c @@ -443,7 +443,8 @@ struct em_cpu_list cpu_list[] = { [1] = {2313909, 0x00, 0x10, ERRATA_X3_2313909}, [2] = {2615812, 0x00, 0x11, ERRATA_X3_2615812}, [3] = {2742421, 0x00, 0x11, ERRATA_X3_2742421}, - [4 ... ERRATA_LIST_END] = UNDEF_ERRATA, + [4] = {2779509, 0x00, 0x11, ERRATA_X3_2779509}, + [5 ... ERRATA_LIST_END] = UNDEF_ERRATA, } }, #endif /* CORTEX_X3_H_INC */