mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 17:44:19 +00:00
Merge "intel: Enable EMAC PHY in Intel FPGA platform" into integration
This commit is contained in:
Sandrine Bailleux
TrustedFirmware Code Review
commit
351d358fed
8 changed files with 91 additions and 10 deletions
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@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2019, Intel Corporation. All rights reserved.
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* Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -20,6 +20,7 @@
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#include "agilex_pinmux.h"
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#include "ccu/ncore_ccu.h"
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#include "qspi/cadence_qspi.h"
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#include "socfpga_emac.h"
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#include "socfpga_handoff.h"
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#include "socfpga_mailbox.h"
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#include "socfpga_private.h"
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@ -72,6 +73,7 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
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socfpga_delay_timer_init();
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init_ncore_ccu();
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socfpga_emac_init();
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init_hard_memory_controller();
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mailbox_init();
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@ -1,6 +1,6 @@
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#
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# Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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# Copyright (c) 2019, Intel Corporation. All rights reserved.
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# Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
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# Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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@ -42,6 +42,7 @@ BL2_SOURCES += \
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plat/intel/soc/common/socfpga_delay_timer.c \
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plat/intel/soc/common/socfpga_image_load.c \
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plat/intel/soc/common/socfpga_storage.c \
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plat/intel/soc/common/soc/socfpga_emac.c \
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plat/intel/soc/common/soc/socfpga_handoff.c \
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plat/intel/soc/common/soc/socfpga_mailbox.c \
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plat/intel/soc/common/soc/socfpga_reset_manager.c \
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@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2019, Intel Corporation. All rights reserved.
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* Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -168,6 +168,14 @@
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#define PLAT_BAUDRATE (115200)
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#define PLAT_UART_CLOCK (100000000)
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/*******************************************************************************
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* PHY related constants
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******************************************************************************/
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#define EMAC0_PHY_MODE PHY_INTERFACE_MODE_RGMII
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#define EMAC1_PHY_MODE PHY_INTERFACE_MODE_RGMII
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#define EMAC2_PHY_MODE PHY_INTERFACE_MODE_RGMII
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/*******************************************************************************
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* System counter frequency related constants
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******************************************************************************/
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24
plat/intel/soc/common/include/socfpga_emac.h
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24
plat/intel/soc/common/include/socfpga_emac.h
Normal file
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@ -0,0 +1,24 @@
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/*
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* Copyright (c) 2020, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SOCFPGA_EMAC_H
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#define SOCFPGA_EMAC_H
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/* EMAC PHY Mode */
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#define PHY_INTERFACE_MODE_GMII_MII 0
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#define PHY_INTERFACE_MODE_RGMII 1
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#define PHY_INTERFACE_MODE_RMII 2
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#define PHY_INTERFACE_MODE_RESET 3
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/* Mask Definitions */
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#define PHY_INTF_SEL_MSK 0x3
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#define FPGAINTF_EN_3_EMAC_MSK(x) (1 << (x * 8))
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void socfpga_emac_init(void);
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#endif /* SOCFPGA_EMAC_H */
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@ -13,6 +13,11 @@
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#define SOCFPGA_SYSMGR_SDMMC 0x28
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#define SOCFPGA_SYSMGR_EMAC_0 0x44
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#define SOCFPGA_SYSMGR_EMAC_1 0x48
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#define SOCFPGA_SYSMGR_EMAC_2 0x4c
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#define SOCFPGA_SYSMGR_FPGAINTF_EN_3 0x70
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#define SOCFPGA_SYSMGR_NOC_TIMEOUT 0xc0
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#define SOCFPGA_SYSMGR_NOC_IDLEREQ_SET 0xc4
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#define SOCFPGA_SYSMGR_NOC_IDLEREQ_CLR 0xc8
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38
plat/intel/soc/common/soc/socfpga_emac.c
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38
plat/intel/soc/common/soc/socfpga_emac.c
Normal file
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@ -0,0 +1,38 @@
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/*
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* Copyright (c) 2020, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <lib/mmio.h>
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#include <platform_def.h>
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#include "socfpga_emac.h"
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#include "socfpga_reset_manager.h"
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#include "socfpga_system_manager.h"
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void socfpga_emac_init(void)
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{
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mmio_setbits_32(SOCFPGA_RSTMGR(PER0MODRST),
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RSTMGR_PER0MODRST_EMAC0 |
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RSTMGR_PER0MODRST_EMAC1 |
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RSTMGR_PER0MODRST_EMAC2);
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mmio_clrsetbits_32(SOCFPGA_SYSMGR(EMAC_0),
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PHY_INTF_SEL_MSK, EMAC0_PHY_MODE);
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mmio_clrsetbits_32(SOCFPGA_SYSMGR(EMAC_1),
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PHY_INTF_SEL_MSK, EMAC1_PHY_MODE);
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mmio_clrsetbits_32(SOCFPGA_SYSMGR(EMAC_2),
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PHY_INTF_SEL_MSK, EMAC2_PHY_MODE);
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mmio_clrbits_32(SOCFPGA_SYSMGR(FPGAINTF_EN_3),
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FPGAINTF_EN_3_EMAC_MSK(0) |
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FPGAINTF_EN_3_EMAC_MSK(1) |
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FPGAINTF_EN_3_EMAC_MSK(2));
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mmio_clrbits_32(SOCFPGA_RSTMGR(PER0MODRST),
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RSTMGR_PER0MODRST_EMAC0 |
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RSTMGR_PER0MODRST_EMAC1 |
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RSTMGR_PER0MODRST_EMAC2);
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}
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@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2019, Intel Corporation. All rights reserved.
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* Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -16,6 +16,7 @@
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#include <lib/xlat_tables/xlat_tables.h>
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#include "qspi/cadence_qspi.h"
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#include "socfpga_emac.h"
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#include "socfpga_handoff.h"
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#include "socfpga_mailbox.h"
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#include "socfpga_private.h"
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@ -69,6 +70,7 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
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console_16550_register(PLAT_UART0_BASE, get_uart_clk(), PLAT_BAUDRATE,
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&console);
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socfpga_emac_init();
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socfpga_delay_timer_init();
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init_hard_memory_controller();
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mailbox_init();
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@ -1,6 +1,6 @@
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#
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# Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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# Copyright (c) 2019, Intel Corporation. All rights reserved.
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# Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
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# Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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@ -42,6 +42,7 @@ BL2_SOURCES += \
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plat/intel/soc/common/socfpga_delay_timer.c \
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plat/intel/soc/common/socfpga_image_load.c \
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plat/intel/soc/common/socfpga_storage.c \
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plat/intel/soc/common/soc/socfpga_emac.c \
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plat/intel/soc/common/soc/socfpga_handoff.c \
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plat/intel/soc/common/soc/socfpga_mailbox.c \
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plat/intel/soc/common/soc/socfpga_reset_manager.c \
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