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feat(st): use newly introduced clock framework

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Replace calls to stm32mp_clk_enable() / stm32mp_clk_disable() /
stm32mp_clk_get_rate() with clk_enable() / clk_disable() /
clk_get_rate().

Change-Id: I15d2ce57b9499211fa522a1b53eeee9cf584c111
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
This commit is contained in:
Yann Gautier 2021-08-30 15:06:54 +02:00 • committed by Yann Gautier
parent 847c6bc8e6
commit 33667d299b
18 changed files with 133 additions and 75 deletions
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5
drivers/st/ddr/stm32mp1_ddr.c
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@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved
* Copyright (C) 2018-2021, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
@ -12,6 +12,7 @@
#include <arch.h>
#include <arch_helpers.h>
#include <common/debug.h>
#include <drivers/clk.h>
#include <drivers/delay_timer.h>
#include <drivers/st/stm32mp_pmic.h>
#include <drivers/st/stm32mp1_ddr.h>
@ -627,7 +628,7 @@ static void stm32mp1_ddr3_dll_off(struct ddr_info *priv)
*/
/* Change Bypass Mode Frequency Range */
if (stm32mp_clk_get_rate(DDRPHYC) < 100000000U) {
if (clk_get_rate(DDRPHYC) < 100000000U) {
mmio_clrbits_32((uintptr_t)&priv->phy->dllgcr,
DDRPHYC_DLLGCR_BPS200);
} else {