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build(intel): add N5X as a new Intel platform
This commit adds a new Intel platform called N5X. This preliminary patch only have Bl31 support. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com> Change-Id: Ib31f9c4a5a0dabdce81c1d5b0d4776188add7195
This commit is contained in:
Sieu Mun Tang
parent
286b96f4bb
commit
325eb35d24
5 changed files with 244 additions and 4 deletions
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@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
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* Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -13,8 +13,10 @@
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#include <common/tbbr/tbbr_img_def.h>
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#include <plat/common/common_def.h>
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/* Platform Type */
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#define PLAT_SOCFPGA_STRATIX10 1
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#define PLAT_SOCFPGA_AGILEX 2
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#define PLAT_SOCFPGA_N5X 3
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/* sysmgr.boot_scratch_cold4 & 5 used for CPU release address for SPL */
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#define PLAT_CPU_RELEASE_ADDR 0xffd12210
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2019, Intel Corporation. All rights reserved.
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* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -134,7 +134,7 @@ int socfpga_bridges_disable(void)
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#if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10
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mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
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~(RSTMGR_FIELD(BRG, DDRSCH) | RSTMGR_FIELD(BRG, FPGA2SOC)));
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#elif PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX
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#else
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mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
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~(RSTMGR_FIELD(BRG, MPFE) | RSTMGR_FIELD(BRG, FPGA2SOC)));
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#endif
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162
plat/intel/soc/n5x/bl31_plat_setup.c
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162
plat/intel/soc/n5x/bl31_plat_setup.c
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@ -0,0 +1,162 @@
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/*
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* Copyright (c) 2020-2022, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <drivers/arm/gicv2.h>
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#include <drivers/ti/uart/uart_16550.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_tables.h>
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#include "socfpga_mailbox.h"
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#include "socfpga_private.h"
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static entry_point_info_t bl32_image_ep_info;
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static entry_point_info_t bl33_image_ep_info;
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entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
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{
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entry_point_info_t *next_image_info;
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next_image_info = (type == NON_SECURE) ?
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&bl33_image_ep_info : &bl32_image_ep_info;
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/* None of the images on this platform can have 0x0 as the entrypoint */
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if (next_image_info->pc) {
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return next_image_info;
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} else {
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return NULL;
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}
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}
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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static console_t console;
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mmio_write_64(PLAT_SEC_ENTRY, 0);
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console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE,
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&console);
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/*
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* Check params passed from BL31 should not be NULL,
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*/
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void *from_bl2 = (void *) arg0;
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bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
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assert(params_from_bl2 != NULL);
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/*
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* Copy BL32 (if populated by BL31) and BL33 entry point information.
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* They are stored in Secure RAM, in BL31's address space.
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*/
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if (params_from_bl2->h.type == PARAM_BL_PARAMS &&
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params_from_bl2->h.version >= VERSION_2) {
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bl_params_node_t *bl_params = params_from_bl2->head;
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while (bl_params != NULL) {
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if (bl_params->image_id == BL33_IMAGE_ID)
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bl33_image_ep_info = *bl_params->ep_info;
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bl_params = bl_params->next_params_info;
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}
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} else {
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struct socfpga_bl31_params *arg_from_bl2 =
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(struct socfpga_bl31_params *) from_bl2;
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assert(arg_from_bl2->h.type == PARAM_BL31);
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assert(arg_from_bl2->h.version >= VERSION_1);
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bl32_image_ep_info = *arg_from_bl2->bl32_ep_info;
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bl33_image_ep_info = *arg_from_bl2->bl33_ep_info;
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}
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SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
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}
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static const interrupt_prop_t s10_interrupt_props[] = {
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PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(GICV2_INTR_GROUP0),
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PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
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};
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static unsigned int target_mask_array[PLATFORM_CORE_COUNT];
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static const gicv2_driver_data_t plat_gicv2_gic_data = {
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.gicd_base = PLAT_INTEL_SOCFPGA_GICD_BASE,
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.gicc_base = PLAT_INTEL_SOCFPGA_GICC_BASE,
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.interrupt_props = s10_interrupt_props,
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.interrupt_props_num = ARRAY_SIZE(s10_interrupt_props),
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.target_masks = target_mask_array,
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.target_masks_num = ARRAY_SIZE(target_mask_array),
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};
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/*******************************************************************************
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* Perform any BL3-1 platform setup code
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******************************************************************************/
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void bl31_platform_setup(void)
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{
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socfpga_delay_timer_init();
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/* Initialize the gic cpu and distributor interfaces */
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gicv2_driver_init(&plat_gicv2_gic_data);
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gicv2_distif_init();
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gicv2_pcpu_distif_init();
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gicv2_cpuif_enable();
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/* Signal secondary CPUs to jump to BL31 (BL2 = U-boot SPL) */
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mmio_write_64(PLAT_CPU_RELEASE_ADDR,
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(uint64_t)plat_secondary_cpus_bl31_entry);
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mailbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL);
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}
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const mmap_region_t plat_dm_mmap[] = {
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MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
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MT_MEMORY | MT_RW | MT_NS),
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MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE,
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MT_DEVICE | MT_RW | MT_NS),
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MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE,
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MT_NON_CACHEABLE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE,
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MT_DEVICE | MT_RW | MT_NS),
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MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE,
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MT_DEVICE | MT_RW | MT_NS),
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{0}
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};
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/*******************************************************************************
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* Perform the very early platform specific architectural setup here. At the
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* moment this is only intializes the mmu in a quick and dirty way.
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******************************************************************************/
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void bl31_plat_arch_setup(void)
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{
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const mmap_region_t bl_regions[] = {
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MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE,
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MT_MEMORY | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
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MT_CODE | MT_SECURE),
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MAP_REGION_FLAT(BL_RO_DATA_BASE,
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BL_RO_DATA_END - BL_RO_DATA_BASE,
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MT_RO_DATA | MT_SECURE),
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#if USE_COHERENT_MEM
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MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
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BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
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MT_DEVICE | MT_RW | MT_SECURE),
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#endif
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{0}
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};
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setup_page_tables(bl_regions, plat_dm_mmap);
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enable_mmu_el3(0);
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}
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27
plat/intel/soc/n5x/include/socfpga_plat_def.h
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27
plat/intel/soc/n5x/include/socfpga_plat_def.h
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@ -0,0 +1,27 @@
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/*
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* Copyright (c) 2020-2022, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLAT_SOCFPGA_DEF_H
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#define PLAT_SOCFPGA_DEF_H
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#include <platform_def.h>
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/* Platform Setting */
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#define PLATFORM_MODEL PLAT_SOCFPGA_N5X
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#define BOOT_SOURCE BOOT_SOURCE_SDMMC
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/* Register Mapping */
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#define SOCFPGA_MMC_REG_BASE U(0xff808000)
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#define SOCFPGA_RSTMGR_REG_BASE U(0xffd11000)
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#define SOCFPGA_SYSMGR_REG_BASE U(0xffd12000)
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#define SOCFPGA_L4_PER_SCR_REG_BASE U(0xffd21000)
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#define SOCFPGA_L4_SYS_SCR_REG_BASE U(0xffd21100)
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#define SOCFPGA_SOC2FPGA_SCR_REG_BASE U(0xffd21200)
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#define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE U(0xffd21300)
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#endif /* PLAT_SOCFPGA_DEF_H */
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49
plat/intel/soc/n5x/platform.mk
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49
plat/intel/soc/n5x/platform.mk
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@ -0,0 +1,49 @@
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#
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# Copyright (c) 2020-2022, Intel Corporation. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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PLAT_INCLUDES := \
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-Iplat/intel/soc/n5x/include/ \
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-Iplat/intel/soc/common/drivers/ \
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-Iplat/intel/soc/common/include/
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# Include GICv2 driver files
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include drivers/arm/gic/v2/gicv2.mk
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DM_GICv2_SOURCES := \
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${GICV2_SOURCES} \
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plat/common/plat_gicv2.c
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PLAT_BL_COMMON_SOURCES := \
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${DM_GICv2_SOURCES} \
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drivers/delay_timer/delay_timer.c \
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drivers/delay_timer/generic_delay_timer.c \
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drivers/ti/uart/aarch64/16550_console.S \
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lib/xlat_tables/aarch64/xlat_tables.c \
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lib/xlat_tables/xlat_tables_common.c \
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plat/intel/soc/common/aarch64/platform_common.c \
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plat/intel/soc/common/aarch64/plat_helpers.S \
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plat/intel/soc/common/socfpga_delay_timer.c
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BL2_SOURCES +=
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BL31_SOURCES += \
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drivers/arm/cci/cci.c \
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lib/cpus/aarch64/aem_generic.S \
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lib/cpus/aarch64/cortex_a53.S \
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plat/common/plat_psci_common.c \
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plat/intel/soc/n5x/bl31_plat_setup.c \
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plat/intel/soc/common/socfpga_psci.c \
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plat/intel/soc/common/socfpga_sip_svc.c \
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plat/intel/soc/common/socfpga_topology.c \
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plat/intel/soc/common/sip/socfpga_sip_fcs.c \
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plat/intel/soc/common/soc/socfpga_mailbox.c \
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plat/intel/soc/common/soc/socfpga_reset_manager.c
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PROGRAMMABLE_RESET_ADDRESS := 0
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BL2_AT_EL3 := 1
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BL2_INV_DCACHE := 0
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MULTI_CONSOLE_API := 1
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USE_COHERENT_MEM := 1
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