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rcar_gen3: plat: Disable IPMMU PV0 cache on E3

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Disable the IPMMU PV0 cache on E3 rev. 1.x .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
This commit is contained in:
Marek Vasut 2018-12-31 16:48:04 +01:00
parent 71430ed465
commit 3238542710
2 changed files with 3 additions and 0 deletions
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1
plat/renesas/rcar/bl2_plat_setup.c
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@ -264,6 +264,7 @@ tlb:
} else if ((product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) ||
(product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER11))) {
mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
mmio_write_32(IPMMUVP0_IMSCTLR, IMSCTLR_DISCACHE);
mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
}

2
plat/renesas/rcar/include/rcar_def.h
View file

@ -231,6 +231,8 @@
#define IPMMUMM_IMSCTLR_ENABLE (0xC0000000U)
#define IPMMUMM_IMAUXCTLR_NMERGE40_BIT (0x01000000U)
#define IMSCTLR_DISCACHE (0xE0000000U)
#define IPMMU_VP0_BASE (0xFE990000U)
#define IPMMUVP0_IMSCTLR (IPMMU_VP0_BASE + 0x0500U)
#define IPMMU_VI0_BASE (0xFEBD0000U)
#define IPMMUVI0_IMSCTLR (IPMMU_VI0_BASE + 0x0500U)
#define IPMMU_VI1_BASE (0xFEBE0000U)