From 31b394552783f959f0e8dfbe8f2cf078c586682e Mon Sep 17 00:00:00 2001 From: Govindraj Raja Date: Fri, 23 Jun 2023 11:28:05 -0500 Subject: [PATCH] chore: rename hunter to a720 Rename cortex_hunter to cortex_a720 Change-Id: Id4e0e2cd47051c2e92b3f16373ea06ef4df1d75f Signed-off-by: Govindraj Raja --- docs/plat/arm/tc/index.rst | 4 +- .../security-advisory-tfv-9.rst | 2 +- .../{cortex_hunter.h => cortex_a720.h} | 20 +++---- .../{cortex_hunter.S => cortex_a720.S} | 56 +++++++++---------- plat/arm/board/arm_fpga/platform.mk | 2 +- plat/arm/board/tc/platform.mk | 2 +- 6 files changed, 43 insertions(+), 43 deletions(-) rename include/lib/cpus/aarch64/{cortex_hunter.h => cortex_a720.h} (51%) rename lib/cpus/aarch64/{cortex_hunter.S => cortex_a720.S} (57%) diff --git a/docs/plat/arm/tc/index.rst b/docs/plat/arm/tc/index.rst index 925befc41..ca9efb6a5 100644 --- a/docs/plat/arm/tc/index.rst +++ b/docs/plat/arm/tc/index.rst @@ -19,7 +19,7 @@ is the CPUs supported as below: - TC0 has support for Cortex A510, Cortex A710 and Cortex X2. (Note TC0 is now deprecated) - TC1 has support for Cortex A510, Cortex Makalu and Cortex X3. -- TC2 has support for Hayes and Hunter Arm CPUs. +- TC2 has support for Hayes and Cortex A720 Arm CPUs. Boot Sequence @@ -58,6 +58,6 @@ Build Procedure (TF-A only) -------------- -*Copyright (c) 2020-2022, Arm Limited. All rights reserved.* +*Copyright (c) 2020-2023, Arm Limited. All rights reserved.* .. _Arm Toolchain: https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/downloads diff --git a/docs/security_advisories/security-advisory-tfv-9.rst b/docs/security_advisories/security-advisory-tfv-9.rst index d73e74b6b..762801d71 100644 --- a/docs/security_advisories/security-advisory-tfv-9.rst +++ b/docs/security_advisories/security-advisory-tfv-9.rst @@ -77,7 +77,7 @@ revisions of Cortex-A73 and Cortex-A75 that implements FEAT_CSV2). +----------------------+ | Cortex-A715 | +----------------------+ -| Cortex-Hunter | +| Cortex-A720 | +----------------------+ | Neoverse-N1 | +----------------------+ diff --git a/include/lib/cpus/aarch64/cortex_hunter.h b/include/lib/cpus/aarch64/cortex_a720.h similarity index 51% rename from include/lib/cpus/aarch64/cortex_hunter.h rename to include/lib/cpus/aarch64/cortex_a720.h index 24bd21760..47bbbc079 100644 --- a/include/lib/cpus/aarch64/cortex_hunter.h +++ b/include/lib/cpus/aarch64/cortex_a720.h @@ -1,26 +1,26 @@ /* - * Copyright (c) 2021-2022, Arm Limited. All rights reserved. + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef CORTEX_HUNTER_H -#define CORTEX_HUNTER_H +#ifndef CORTEX_A720_H +#define CORTEX_A720_H -#define CORTEX_HUNTER_MIDR U(0x410FD810) +#define CORTEX_A720_MIDR U(0x410FD810) -/* Cortex Hunter loop count for CVE-2022-23960 mitigation */ -#define CORTEX_HUNTER_BHB_LOOP_COUNT U(132) +/* Cortex A720 loop count for CVE-2022-23960 mitigation */ +#define CORTEX_A720_BHB_LOOP_COUNT U(132) /******************************************************************************* * CPU Extended Control register specific definitions ******************************************************************************/ -#define CORTEX_HUNTER_CPUECTLR_EL1 S3_0_C15_C1_4 +#define CORTEX_A720_CPUECTLR_EL1 S3_0_C15_C1_4 /******************************************************************************* * CPU Power Control register specific definitions ******************************************************************************/ -#define CORTEX_HUNTER_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define CORTEX_HUNTER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) +#define CORTEX_A720_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) -#endif /* CORTEX_HUNTER_H */ +#endif /* CORTEX_A720_H */ diff --git a/lib/cpus/aarch64/cortex_hunter.S b/lib/cpus/aarch64/cortex_a720.S similarity index 57% rename from lib/cpus/aarch64/cortex_hunter.S rename to lib/cpus/aarch64/cortex_a720.S index 973637e44..529ab50b7 100644 --- a/lib/cpus/aarch64/cortex_hunter.S +++ b/lib/cpus/aarch64/cortex_a720.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022, Arm Limited. All rights reserved. + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,23 +7,23 @@ #include #include #include -#include +#include #include #include #include "wa_cve_2022_23960_bhb_vector.S" /* Hardware handled coherency */ #if HW_ASSISTED_COHERENCY == 0 -#error "Cortex Hunter must be compiled with HW_ASSISTED_COHERENCY enabled" +#error "Cortex A720 must be compiled with HW_ASSISTED_COHERENCY enabled" #endif /* 64-bit only core */ #if CTX_INCLUDE_AARCH32_REGS == 1 -#error "Cortex Hunter supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#error "Cortex A720 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif #if WORKAROUND_CVE_2022_23960 - wa_cve_2022_23960_bhb_vector_table CORTEX_HUNTER_BHB_LOOP_COUNT, cortex_hunter + wa_cve_2022_23960_bhb_vector_table CORTEX_A720_BHB_LOOP_COUNT, cortex_a720 #endif /* WORKAROUND_CVE_2022_23960 */ func check_errata_cve_2022_23960 @@ -35,44 +35,44 @@ func check_errata_cve_2022_23960 ret endfunc check_errata_cve_2022_23960 -func cortex_hunter_reset_func +func cortex_a720_reset_func /* Disable speculative loads */ msr SSBS, xzr #if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 /* - * The Cortex Hunter generic vectors are overridden to apply errata + * The Cortex A720 generic vectors are overridden to apply errata * mitigation on exception entry from lower ELs. */ - adr x0, wa_cve_vbar_cortex_hunter + adr x0, wa_cve_vbar_cortex_a720 msr vbar_el3, x0 #endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ isb ret -endfunc cortex_hunter_reset_func +endfunc cortex_a720_reset_func /* ---------------------------------------------------- * HW will do the cache maintenance while powering down * ---------------------------------------------------- */ -func cortex_hunter_core_pwr_dwn +func cortex_a720_core_pwr_dwn /* --------------------------------------------------- * Enable CPU power down bit in power control register * --------------------------------------------------- */ - mrs x0, CORTEX_HUNTER_CPUPWRCTLR_EL1 - orr x0, x0, #CORTEX_HUNTER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT - msr CORTEX_HUNTER_CPUPWRCTLR_EL1, x0 + mrs x0, CORTEX_A720_CPUPWRCTLR_EL1 + orr x0, x0, #CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + msr CORTEX_A720_CPUPWRCTLR_EL1, x0 isb ret -endfunc cortex_hunter_core_pwr_dwn +endfunc cortex_a720_core_pwr_dwn #if REPORT_ERRATA /* - * Errata printing function for Cortex Hunter. Must follow AAPCS. + * Errata printing function for Cortex A720. Must follow AAPCS. */ -func cortex_hunter_errata_report +func cortex_a720_errata_report stp x8, x30, [sp, #-16]! bl cpu_get_rev_var @@ -82,15 +82,15 @@ func cortex_hunter_errata_report * Report all errata. The revision-variant information is passed to * checking functions of each errata. */ - report_errata WORKAROUND_CVE_2022_23960, cortex_hunter, cve_2022_23960 + report_errata WORKAROUND_CVE_2022_23960, cortex_a720, cve_2022_23960 ldp x8, x30, [sp], #16 ret -endfunc cortex_hunter_errata_report +endfunc cortex_a720_errata_report #endif /* --------------------------------------------- - * This function provides Cortex Hunter-specific + * This function provides Cortex A720-specific * register information for crash reporting. * It needs to return with x6 pointing to * a list of register names in ascii and @@ -98,16 +98,16 @@ endfunc cortex_hunter_errata_report * reported. * --------------------------------------------- */ -.section .rodata.cortex_hunter_regs, "aS" -cortex_hunter_regs: /* The ascii list of register names to be reported */ +.section .rodata.cortex_a720_regs, "aS" +cortex_a720_regs: /* The ascii list of register names to be reported */ .asciz "cpuectlr_el1", "" -func cortex_hunter_cpu_reg_dump - adr x6, cortex_hunter_regs - mrs x8, CORTEX_HUNTER_CPUECTLR_EL1 +func cortex_a720_cpu_reg_dump + adr x6, cortex_a720_regs + mrs x8, CORTEX_A720_CPUECTLR_EL1 ret -endfunc cortex_hunter_cpu_reg_dump +endfunc cortex_a720_cpu_reg_dump -declare_cpu_ops cortex_hunter, CORTEX_HUNTER_MIDR, \ - cortex_hunter_reset_func, \ - cortex_hunter_core_pwr_dwn +declare_cpu_ops cortex_a720, CORTEX_A720_MIDR, \ + cortex_a720_reset_func, \ + cortex_a720_core_pwr_dwn diff --git a/plat/arm/board/arm_fpga/platform.mk b/plat/arm/board/arm_fpga/platform.mk index d6622c046..3d2f8be20 100644 --- a/plat/arm/board/arm_fpga/platform.mk +++ b/plat/arm/board/arm_fpga/platform.mk @@ -61,6 +61,7 @@ else FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a510.S \ lib/cpus/aarch64/cortex_a710.S \ lib/cpus/aarch64/cortex_a715.S \ + lib/cpus/aarch64/cortex_a720.S \ lib/cpus/aarch64/cortex_x3.S \ lib/cpus/aarch64/cortex_x4.S \ lib/cpus/aarch64/neoverse_n_common.S \ @@ -68,7 +69,6 @@ else lib/cpus/aarch64/neoverse_n2.S \ lib/cpus/aarch64/neoverse_v1.S \ lib/cpus/aarch64/cortex_hayes.S \ - lib/cpus/aarch64/cortex_hunter.S \ lib/cpus/aarch64/cortex_chaberton.S \ lib/cpus/aarch64/cortex_blackhawk.S diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk index 1bde94e8e..4faa98fcf 100644 --- a/plat/arm/board/tc/platform.mk +++ b/plat/arm/board/tc/platform.mk @@ -79,7 +79,7 @@ endif # CPU libraries for TARGET_PLATFORM=2 ifeq (${TARGET_PLATFORM}, 2) TC_CPU_SOURCES += lib/cpus/aarch64/cortex_hayes.S \ - lib/cpus/aarch64/cortex_hunter.S \ + lib/cpus/aarch64/cortex_a720.S \ lib/cpus/aarch64/cortex_x4.S endif