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Merge "feat(tc): add devicetree node for AP/RSE MHU" into integration

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This commit is contained in:
Manish Pandey 2024-12-13 14:30:08 +01:00 • committed by TrustedFirmware Code Review
commit 31a223cbb1
3 changed files with 40 additions and 0 deletions
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34
fdts/tc3-4-base.dtsi
View file

@ -52,6 +52,31 @@
}; };
}; };
rse_mbox_db_rx: mhu@RSE_MHU_RX_ADDR {
compatible = MHU_RX_COMPAT;
reg = <0x0 ADDRESSIFY(RSE_MHU_RX_ADDR) 0x0 MHU_OFFSET>;
clocks = <&soc_refclk>;
clock-names = "apb_pclk";
#mbox-cells = <MHU_MBOX_CELLS>;
interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = MHU_RX_INT_NAME;
#if TARGET_FLAVOUR_FPGA
status = "disabled";
#endif
};
rse_mbox_db_tx: mhu@RSE_MHU_TX_ADDR {
compatible = MHU_TX_COMPAT;
reg = <0x0 ADDRESSIFY(RSE_MHU_TX_ADDR) 0x0 MHU_OFFSET>;
clocks = <&soc_refclk>;
clock-names = "apb_pclk";
#mbox-cells = <MHU_MBOX_CELLS>;
interrupt-names = MHU_TX_INT_NAME;
#if TARGET_FLAVOUR_FPGA
status = "disabled";
#endif
};
gic: interrupt-controller@GIC_CTRL_ADDR { gic: interrupt-controller@GIC_CTRL_ADDR {
ppi-partitions { ppi-partitions {
ppi_partition_little: interrupt-partition-0 { ppi_partition_little: interrupt-partition-0 {
@ -80,6 +105,15 @@
mboxes = <&mbox_db_tx 0 0 0 &mbox_db_rx 0 0 0 &mbox_db_rx 0 0 1>; mboxes = <&mbox_db_tx 0 0 0 &mbox_db_rx 0 0 0 &mbox_db_rx 0 0 1>;
shmem = <&cpu_scp_scmi_a2p &cpu_scp_scmi_p2a>; shmem = <&cpu_scp_scmi_a2p &cpu_scp_scmi_p2a>;
}; };
rse {
compatible = "arm,rse";
mbox-names = "tx", "rx";
mboxes = <&rse_mbox_db_tx 0 0 0>, <&rse_mbox_db_rx 0 0 0>;
#if TARGET_FLAVOUR_FPGA
status = "disabled";
#endif
};
}; };
dsu-pmu { dsu-pmu {

3
fdts/tc3.dts
View file

@ -13,6 +13,9 @@
#define MHU_TX_ADDR 46040000 /* hex */ #define MHU_TX_ADDR 46040000 /* hex */
#define MHU_RX_ADDR 46140000 /* hex */ #define MHU_RX_ADDR 46140000 /* hex */
#define RSE_MHU_TX_ADDR 49010000 /* hex */
#define RSE_MHU_RX_ADDR 49110000 /* hex */
#define LIT_CPU_PMU_COMPATIBLE "arm,cortex-a520-pmu" #define LIT_CPU_PMU_COMPATIBLE "arm,cortex-a520-pmu"
#define MID_CPU_PMU_COMPATIBLE "arm,cortex-a725-pmu" #define MID_CPU_PMU_COMPATIBLE "arm,cortex-a725-pmu"
#define BIG_CPU_PMU_COMPATIBLE "arm,cortex-x925-pmu" #define BIG_CPU_PMU_COMPATIBLE "arm,cortex-x925-pmu"

3
fdts/tc4.dts
View file

@ -17,6 +17,9 @@
#define MID_CPU_PMU_COMPATIBLE "arm,armv8-pmuv3" #define MID_CPU_PMU_COMPATIBLE "arm,armv8-pmuv3"
#define BIG_CPU_PMU_COMPATIBLE "arm,armv8-pmuv3" #define BIG_CPU_PMU_COMPATIBLE "arm,armv8-pmuv3"
#define RSE_MHU_TX_ADDR 49020000 /* hex */
#define RSE_MHU_RX_ADDR 49030000 /* hex */
#define ETHERNET_ADDR 64000000 #define ETHERNET_ADDR 64000000
#define ETHERNET_INT 799 #define ETHERNET_INT 799