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Implement {spe,sve}_supported() helpers and refactor code
Implement helpers to test if the core supports SPE/SVE. We have a similar helper for AMU and this patch makes all extensions consistent in their implementation. Change-Id: I3e6f7522535ca358259ad142550b19fcb883ca67 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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4 changed files with 135 additions and 129 deletions
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -7,6 +7,7 @@
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#ifndef __SPE_H__
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#ifndef __SPE_H__
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#define __SPE_H__
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#define __SPE_H__
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int spe_supported(void);
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void spe_enable(int el2_unused);
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void spe_enable(int el2_unused);
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void spe_disable(void);
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void spe_disable(void);
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -7,6 +7,7 @@
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#ifndef __SVE_H__
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#ifndef __SVE_H__
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#define __SVE_H__
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#define __SVE_H__
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int sve_supported(void);
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void sve_enable(int el2_unused);
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void sve_enable(int el2_unused);
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#endif /* __SVE_H__ */
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#endif /* __SVE_H__ */
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/*
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -14,14 +14,21 @@
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*/
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*/
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#define psb_csync() asm volatile("hint #17")
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#define psb_csync() asm volatile("hint #17")
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void spe_enable(int el2_unused)
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int spe_supported(void)
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{
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{
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uint64_t features;
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uint64_t features;
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features = read_id_aa64dfr0_el1() >> ID_AA64DFR0_PMS_SHIFT;
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features = read_id_aa64dfr0_el1() >> ID_AA64DFR0_PMS_SHIFT;
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if ((features & ID_AA64DFR0_PMS_MASK) == 1) {
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return (features & ID_AA64DFR0_PMS_MASK) == 1;
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}
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void spe_enable(int el2_unused)
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{
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uint64_t v;
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uint64_t v;
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if (!spe_supported())
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return;
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if (el2_unused) {
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if (el2_unused) {
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/*
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/*
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* MDCR_EL2.TPMS (ARM v8.2): Do not trap statistical
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* MDCR_EL2.TPMS (ARM v8.2): Do not trap statistical
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@ -46,16 +53,14 @@ void spe_enable(int el2_unused)
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v |= MDCR_NSPB(MDCR_NSPB_EL1);
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v |= MDCR_NSPB(MDCR_NSPB_EL1);
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write_mdcr_el3(v);
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write_mdcr_el3(v);
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}
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}
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}
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void spe_disable(void)
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void spe_disable(void)
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{
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{
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uint64_t features;
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features = read_id_aa64dfr0_el1() >> ID_AA64DFR0_PMS_SHIFT;
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if ((features & ID_AA64DFR0_PMS_MASK) == 1) {
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uint64_t v;
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uint64_t v;
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if (!spe_supported())
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return;
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/* Drain buffered data */
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/* Drain buffered data */
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psb_csync();
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psb_csync();
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dsbnsh();
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dsbnsh();
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@ -66,19 +71,15 @@ void spe_disable(void)
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write_pmblimitr_el1(v);
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write_pmblimitr_el1(v);
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isb();
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isb();
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}
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}
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}
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static void *spe_drain_buffers_hook(const void *arg)
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static void *spe_drain_buffers_hook(const void *arg)
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{
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{
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uint64_t features;
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if (!spe_supported())
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return (void *)-1;
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features = read_id_aa64dfr0_el1() >> ID_AA64DFR0_PMS_SHIFT;
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if ((features & ID_AA64DFR0_PMS_MASK) == 1) {
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/* Drain buffered data */
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/* Drain buffered data */
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psb_csync();
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psb_csync();
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dsbnsh();
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dsbnsh();
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}
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return 0;
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return 0;
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}
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}
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -9,14 +9,21 @@
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#include <pubsub.h>
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#include <pubsub.h>
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#include <sve.h>
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#include <sve.h>
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static void *disable_sve_hook(const void *arg)
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int sve_supported(void)
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{
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{
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uint64_t features;
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uint64_t features;
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features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_SVE_SHIFT;
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features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_SVE_SHIFT;
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if ((features & ID_AA64PFR0_SVE_MASK) == 1) {
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return (features & ID_AA64PFR0_SVE_MASK) == 1;
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}
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static void *disable_sve_hook(const void *arg)
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{
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uint64_t cptr;
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uint64_t cptr;
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if (!sve_supported())
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return (void *)-1;
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/*
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/*
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* Disable SVE, SIMD and FP access for the Secure world.
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* Disable SVE, SIMD and FP access for the Secure world.
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* As the SIMD/FP registers are part of the SVE Z-registers, any
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* As the SIMD/FP registers are part of the SVE Z-registers, any
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@ -32,18 +39,16 @@ static void *disable_sve_hook(const void *arg)
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* No explicit ISB required here as ERET to switch to Secure
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* No explicit ISB required here as ERET to switch to Secure
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* world covers it
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* world covers it
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*/
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*/
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}
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return 0;
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return 0;
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}
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}
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static void *enable_sve_hook(const void *arg)
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static void *enable_sve_hook(const void *arg)
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{
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{
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uint64_t features;
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features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_SVE_SHIFT;
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if ((features & ID_AA64PFR0_SVE_MASK) == 1) {
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uint64_t cptr;
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uint64_t cptr;
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if (!sve_supported())
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return (void *)-1;
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/*
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/*
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* Enable SVE, SIMD and FP access for the Non-secure world.
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* Enable SVE, SIMD and FP access for the Non-secure world.
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*/
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*/
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* No explicit ISB required here as ERET to switch to Non-secure
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* No explicit ISB required here as ERET to switch to Non-secure
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* world covers it
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* world covers it
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*/
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*/
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}
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return 0;
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return 0;
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}
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}
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void sve_enable(int el2_unused)
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void sve_enable(int el2_unused)
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{
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{
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uint64_t features;
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features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_SVE_SHIFT;
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if ((features & ID_AA64PFR0_SVE_MASK) == 1) {
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uint64_t cptr;
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uint64_t cptr;
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if (!sve_supported())
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return;
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#if CTX_INCLUDE_FPREGS
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#if CTX_INCLUDE_FPREGS
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/*
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/*
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* CTX_INCLUDE_FPREGS is not supported on SVE enabled systems.
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* CTX_INCLUDE_FPREGS is not supported on SVE enabled systems.
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* Non-secure world covers it.
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* Non-secure world covers it.
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*/
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*/
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}
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}
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}
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SUBSCRIBE_TO_EVENT(cm_exited_normal_world, disable_sve_hook);
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SUBSCRIBE_TO_EVENT(cm_exited_normal_world, disable_sve_hook);
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SUBSCRIBE_TO_EVENT(cm_entering_normal_world, enable_sve_hook);
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SUBSCRIBE_TO_EVENT(cm_entering_normal_world, enable_sve_hook);
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