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Merge "feat(zynqmp): add pin group for lower qspi interface" into integration

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Manish V Badarkhe 2025-03-21 12:30:41 +01:00 • committed by TrustedFirmware Code Review
commit 2f4bcc08bb
2 changed files with 12 additions and 3 deletions
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12
plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
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@ -1,6 +1,6 @@
/* /*
* Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -123,7 +123,7 @@ static struct pinctrl_function pinctrl_functions[MAX_FUNCTION] = {
.name = "qspi0", .name = "qspi0",
.regval = 0x02, .regval = 0x02,
.group_base = PINCTRL_GRP_QSPI0_0, .group_base = PINCTRL_GRP_QSPI0_0,
.group_size = PINCTRL_GRP_QSPI0_0 - PINCTRL_GRP_QSPI0_0 + 1U, .group_size = PINCTRL_GRP_QSPI0_1 - PINCTRL_GRP_QSPI0_0 + 1U,
}, },
[PINCTRL_FUNC_QSPI_FBCLK] = { [PINCTRL_FUNC_QSPI_FBCLK] = {
.name = "qspi_fbclk", .name = "qspi_fbclk",
@ -135,7 +135,7 @@ static struct pinctrl_function pinctrl_functions[MAX_FUNCTION] = {
.name = "qspi_ss", .name = "qspi_ss",
.regval = 0x02, .regval = 0x02,
.group_base = PINCTRL_GRP_QSPI_SS, .group_base = PINCTRL_GRP_QSPI_SS,
.group_size = PINCTRL_GRP_QSPI_SS - PINCTRL_GRP_QSPI_SS + 1U, .group_size = PINCTRL_GRP_QSPI_SS_1 - PINCTRL_GRP_QSPI_SS + 1U,
}, },
[PINCTRL_FUNC_SPI0] = { [PINCTRL_FUNC_SPI0] = {
.name = "spi0", .name = "spi0",
@ -383,6 +383,7 @@ static struct zynqmp_pin_group zynqmp_pin_groups[MAX_PIN] = {
[PINCTRL_PIN_0] = { [PINCTRL_PIN_0] = {
.groups = &((uint16_t []) { .groups = &((uint16_t []) {
PINCTRL_GRP_QSPI0_0, PINCTRL_GRP_QSPI0_0,
PINCTRL_GRP_QSPI0_1,
PINCTRL_GRP_RESERVED, PINCTRL_GRP_RESERVED,
PINCTRL_GRP_RESERVED, PINCTRL_GRP_RESERVED,
PINCTRL_GRP_TESTSCAN0_0, PINCTRL_GRP_TESTSCAN0_0,
@ -401,6 +402,7 @@ static struct zynqmp_pin_group zynqmp_pin_groups[MAX_PIN] = {
[PINCTRL_PIN_1] = { [PINCTRL_PIN_1] = {
.groups = &((uint16_t []) { .groups = &((uint16_t []) {
PINCTRL_GRP_QSPI0_0, PINCTRL_GRP_QSPI0_0,
PINCTRL_GRP_QSPI0_1,
PINCTRL_GRP_RESERVED, PINCTRL_GRP_RESERVED,
PINCTRL_GRP_RESERVED, PINCTRL_GRP_RESERVED,
PINCTRL_GRP_TESTSCAN0_0, PINCTRL_GRP_TESTSCAN0_0,
@ -419,6 +421,7 @@ static struct zynqmp_pin_group zynqmp_pin_groups[MAX_PIN] = {
[PINCTRL_PIN_2] = { [PINCTRL_PIN_2] = {
.groups = &((uint16_t []) { .groups = &((uint16_t []) {
PINCTRL_GRP_QSPI0_0, PINCTRL_GRP_QSPI0_0,
PINCTRL_GRP_QSPI0_1,
PINCTRL_GRP_RESERVED, PINCTRL_GRP_RESERVED,
PINCTRL_GRP_RESERVED, PINCTRL_GRP_RESERVED,
PINCTRL_GRP_TESTSCAN0_0, PINCTRL_GRP_TESTSCAN0_0,
@ -437,6 +440,7 @@ static struct zynqmp_pin_group zynqmp_pin_groups[MAX_PIN] = {
[PINCTRL_PIN_3] = { [PINCTRL_PIN_3] = {
.groups = &((uint16_t []) { .groups = &((uint16_t []) {
PINCTRL_GRP_QSPI0_0, PINCTRL_GRP_QSPI0_0,
PINCTRL_GRP_QSPI0_1,
PINCTRL_GRP_RESERVED, PINCTRL_GRP_RESERVED,
PINCTRL_GRP_RESERVED, PINCTRL_GRP_RESERVED,
PINCTRL_GRP_TESTSCAN0_0, PINCTRL_GRP_TESTSCAN0_0,
@ -455,6 +459,7 @@ static struct zynqmp_pin_group zynqmp_pin_groups[MAX_PIN] = {
[PINCTRL_PIN_4] = { [PINCTRL_PIN_4] = {
.groups = &((uint16_t []) { .groups = &((uint16_t []) {
PINCTRL_GRP_QSPI0_0, PINCTRL_GRP_QSPI0_0,
PINCTRL_GRP_QSPI0_1,
PINCTRL_GRP_RESERVED, PINCTRL_GRP_RESERVED,
PINCTRL_GRP_RESERVED, PINCTRL_GRP_RESERVED,
PINCTRL_GRP_TESTSCAN0_0, PINCTRL_GRP_TESTSCAN0_0,
@ -473,6 +478,7 @@ static struct zynqmp_pin_group zynqmp_pin_groups[MAX_PIN] = {
[PINCTRL_PIN_5] = { [PINCTRL_PIN_5] = {
.groups = &((uint16_t []) { .groups = &((uint16_t []) {
PINCTRL_GRP_QSPI_SS, PINCTRL_GRP_QSPI_SS,
PINCTRL_GRP_QSPI_SS_1,
PINCTRL_GRP_RESERVED, PINCTRL_GRP_RESERVED,
PINCTRL_GRP_RESERVED, PINCTRL_GRP_RESERVED,
PINCTRL_GRP_TESTSCAN0_0, PINCTRL_GRP_TESTSCAN0_0,

3
plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.h
View file

@ -1,5 +1,6 @@
/* /*
* Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -184,7 +185,9 @@ enum {
PINCTRL_GRP_MDIO2_0, PINCTRL_GRP_MDIO2_0,
PINCTRL_GRP_MDIO3_0, PINCTRL_GRP_MDIO3_0,
PINCTRL_GRP_QSPI0_0, PINCTRL_GRP_QSPI0_0,
PINCTRL_GRP_QSPI0_1,
PINCTRL_GRP_QSPI_SS, PINCTRL_GRP_QSPI_SS,
PINCTRL_GRP_QSPI_SS_1,
PINCTRL_GRP_QSPI_FBCLK, PINCTRL_GRP_QSPI_FBCLK,
PINCTRL_GRP_SPI0_0, PINCTRL_GRP_SPI0_0,
PINCTRL_GRP_SPI0_1, PINCTRL_GRP_SPI0_1,